Abstract: A general purpose interpolator-decimator circuit for increasing or decreasing the sampling rate of a digital signal by a factor L/M, where L and M are integers, is disclosed. The circuit includes means for determining each output sample by multiplying a sequence of previous input samples by a set of coefficients and accumulating the resulting products. L sets of coefficients, in which each coefficient is a function of the factors L and M, are stored in a specific sequence which permits sequential addressing of both the coefficients and input signal samples. A multistage decimator cascaded with a multistage interpolator to effect a narrow-band FIR filter is also disclosed.

Abstract: In a multitone pushbutton dial array each switch in the array has a variable impedance coupling between a fixedly mounted conductive plate and a movable conductive plate spaced apart from the fixedly mounted plate. Digitally synthesized signals having a predetermined phase and frequency are sequentially and recurrently used to scan interconnected columns of movable plates in the pushbutton dial array. Signals having an opposite phase from the scanning signals are continuously applied to the fixedly mounted plates. When a pushbutton is depressed variable impedance coupled summation signals are produced and these signals have a phase which is opposite to that of signals coupled to the detector from an unoperated switch. The detected digital signals are used to generate digital multitone row and column frequency signals. These digital row and column signals are converted to analog form and are transmitted to a telephone central office as a dialed digit code.

Abstract: A self latching and unlatching connector assembly includes first and second connectors having mating electrical contacts. The first connector has affixed thereto a pair of latch members. The second connector is mounted in an assembly which includes upper and lower shell halves, each of which has a groove therein for engaging a mounting flange on the connector. A pair of levers, each having first and second arms, are mounted on a pair of pivots which are integral with the lower shell half. One arm of each of these levers engages one of a pair of spring latches, each of which has provision at one end thereof for latching the second connector assembly to the first connector latch members. A sleeve having a pair of locking pins affixed thereto fits over the two mated shell halves. To effect disconnection the sleeve is grasped at any position on its periphery and pulled.

Abstract: In many digital processing systems it is necessary to delay an applied signal by a time interval which is not an integer multiple of the system sampling period. Disclosed herein is a digital phase shifter which utilizes a particular digital filtering scheme for supplying virtually any predetermined delay. Although conceptually related to the digital concepts of phase shift by interpolation and decimation in which the sampling rate is first increased and then restored to the original sampling rate after effecting the desired phase shift, the disclosed phase shifter operates entirely at the system sampling rate. This is accomplished by establishing a specific predetermined subset of digital filter coefficients and combining the coefficients with the input signal samples in a multiplier and accumulator circuit.