Abstract: A data processor having an integral timer including a clock generator producing a specific frequency output comprises a counter chain having an input and output thereof for supplying a fixed frequency divide function. A programmable prescaler couples the clock generator output to the counter chain input for providing a predetermined divisor input to the counter chain. A postscaler operates in consonance with the programmable prescaler coupled to the counter chain output for providing a timer output compensated for the predetermined divisor input. In operation, the timer output has a frequency bearing a constant relationship to the clock generator output frequency independent of the predetermined divisor input of the programmable prescaler.

Abstract: A buffer circuit comprising a current source transistor, a switching transistor and a current sink transistor coupled in series is provided. Control electrodes of the switching transistor and current sink transistor are directly connected and coupled to an input voltage. The buffer circuit has an accurate switchpoint voltage which is substantially process and temperature independent, and the circuit does not consume power for input voltages having low and high CMOS levels.

Abstract: A typical feature of a data processor is a bounds check. A bounds check is achieved when a determination is made as to whether a check value, typically an address or datum, is within predetermined bounds. Such check values may be signed or unsigned. By requiring that the upper bound be numerically larger than the lower bound for doing a signed check, and requiring that the upper bound be logically larger than the lower bound for doing an unsigned check, the bounds check is performed by the data processor without the need of receiving a signal which informs the data processor in advance as to whether the check is to be signed or unsigned.

Abstract: A semiconductor die surface heater and a method of using the die surface heater as a wire bonding assembly are provided. In the preferred form, the semiconductor die surface heater comprises two heaters. A preheater heats the surface of a semiconductor die which is attached to a lead frame via radiant energy. A clamp which positions both the semiconductor die and lead frame during the wire bonding has a window portion with a surface clamp heater for heating at least the portion of the clamp around the window.

Abstract: An envelope detector comprising an absolute value detection portion and a filter portion implemented in switched capacitor technology with common circuit elements is provided. The absolute value of an input signal is obtained and an amplitude envelope is filtered therefrom. The absolute value detection portions and the filter portions share the same integrating operational amplifier to perform the envelope detection.

Abstract: An MOS full adder circuit having a sum circuit portion and a carry circuit portion is provided. In an embodiment utilizing transistors of opposite conductivity type, both the sum and carry circuits are symmetrical, thereby simplifying the physical layout of the full adder during fabrication.

Abstract: An I/O circuit is provided having a terminal for either receiving an input signal or providing an output signal. In one form, the circuit may be utilized in a system with multiple I/O circuits coupled via a two-wire interconnection having a common ground conductor throughout the system. Input signal levels are sensed within a narrow voltage range referenced, in part, to the V.sub.be of a bipolar transistor and independent of the power supply voltage of other interconnected circuits. In response to an enable signal, a differential amplifier provides an output drive signal proportional to the difference between the signal at the terminal and a reference voltage. The output drive signal is coupled to a driver stage which provides a predetermined limited current at the terminal, thereby providing an output signal. A voltage limiter allows the circuit to use bipolar transistors in a P-well CMOS process and to receive input voltages greater than the supply voltage of the circuit.

Abstract: A CMOS static RAM, which has P channel transistors formed in a second polysilicon layer, N channel transistors formed in the substrate, and gates of both the N channel and P channel transistors formed in a first polysilicon layers, requires that ohmic contact be made between semiconductor material of differing conductivity type. The first polysilicon layer is N-type, and the second polysilicon layer is P-type. Ohmic contact therebetween is achieved by providing a silicide layer which is between these two layers and in physical contact with both. Ohmic contact between N-type regions in the substrate and the second polysilicon layer is similarly achieved by sandwiching silicide therebetween.

Abstract: A microprocessor is disclosed having a bus controller which is capable of automatically performing multiple bus cycles in response to a multi-cycle signal received from the control unit. The bus controller includes means for automatically incrementing the access address provided by the control unit, and for controlling the transfer of the data between the bus and respective destinations in the control units.

Abstract: A write protection circuit for a control register includes a first logic circuit which provides a write enable signal to the control register in response to simultaneously receiving a register select signal, a write control signal and an enable signal. A second logic circuit provides the enable signal to the first logic circuit only until the first logic circuit first provides the write enable signal. The second logic circuit will also cease to provide the enable signal in response to a time-out signal. In response to either a reset signal or a test signal, the second logic circuit will again provide the enable signal.

Abstract: An arbitration circuit for asynchronously arbitrating between refreshing memory and performing a non-refresh memory cycle in a memory system having memory cycle generating circuitry. Arbitration circuitry comprising logic circuitry, a clocked storage device and delay circuits which are coupled to memory cycle generating circuitry for performing an arbitration decision for a memory during an immediately preceding memory cycle. The arbitration circuitry time overlaps an arbitration operation with a memory cycle operation during a first memory cycle, thereby improving data rate for an adjacent second memory cycle.

Abstract: A buffer circuit is provided for buffering an input clock signal having TTL voltage levels to provide an output clock signal having MOS voltage levels. A reference voltage portion provides an accurate bias voltage to a first node. A voltage translation portion is coupled between an input and the first node. An inverter portion has a first input connected to the first node, a second input for receiving the input clock signal, and an output for providing the output clock signal. A clamping portion is connected to the first node to minimize the bias voltage potential.

Abstract: A fully differential gain stage having high gain and common-mode feedback is provided with minimal circuitry. Differential input transistors adapted to receive differential input voltages are coupled to load transistors. During a first time period, the gain stage is placed in unity gain and the load transistors are configured as diodes. Charge storage devices are charged during the first time period with a charge which is proportional to both the current of a current supply and the physical dimensions of the load transistors. During a second time period, the charge storage devices provide a bias voltage to the load transistors which maintains the common-mode output voltage at a predetermined value. During the second time period, the gain stage is configured for high gain operation.

Abstract: A memory circuit which has both RAM cells and ROM cells along a common row has a ROM cell which is directly connected to the word line for the row but which is not enabled when a logic state opposite to that represented by the ROM cell is attempted to be written into the ROM cell. Consequently the only word line required for enabling the ROM cells is the word line which enables the RAM cells.

Abstract: An X.times.Y bit array multiplier/accumulator circuit is provided for adding an input number having (X+Y) bits to an (X+Y) bit product of an X bit number and a Y bit number, where X and Y are integers. Modified Booth's algorithm is implemented with an array structure which maintains a regular and systematic structure. The array structure uses adders and multiplexers in a predetermined column and row arrangement. Propagation delay is minimized while utilizing the modified Booth's algorithm by using a sum skipping technique and by using inverting logic properties of adders. Sign bit extension is provided by additional logic circuitry and signed/unsigned modes of operation are provided.

Abstract: A fusible link having a programmable floating gate transistor in a first active region uses an extension of the floating gate to a second active region to provide electrons to the floating gate by the method of tunneling or the method of hot electron injection to avoid applying high voltage to the output terminals of the programmable floating gate transistor.

Abstract: An operational amplifier having differential inputs and differential outputs with a predetermined common-mode output voltage independent of common-mode input voltage and input voltage variation is provided. D.C. common-mode feedback is utilized to provide a differential amplifier having a precise common-mode output voltage.

Abstract: A method for allowing the user of a data processor having a power-down instruction to selectively disable the power-down instruction. In the preferred circuit, the user stores a special code in a control register indicating that the power-down instruction is to be disabled. Upon a power-down instruction being subsequently executed, the processor is precluded by the code from turning off the oscillator which provides the system clocks. The processor thus proceeds to the next instruction as if the power-down instruction were a "no-operation" instruction.

Abstract: A read-only-memory (ROM) having a plurality of enhancement and depletion transistors selectively arranged in an array with the gates of the transistors in each row connected in common to form word lines, and the current paths of the transistors in each column connected in series to form bit lines. The word lines are precharged and then allowed to float. The bit lines are then precharged, bootstrapping the word lines above the precharge level. A selected one of the word lines is thereafter discharged before one end of each of the bit lines is connected to ground. A selected bit line will either remain precharged or be discharged depending upon the type of transistor at the intersection of the selected word and bit lines.

Abstract: A shift register bit with first and second masters and a slave receives clocked data on the first master from two inputs. After data has been received by the first master, data is coupled from the first master to the second master. In the event that both clocked inputs are operative, the second master is coupled to the slave. One of the inputs is given priority. The other input is disabled. At a predetermined time the second master is decoupled from the slave and the first master is coupled back to the slave.