Abstract: A multi-processor AC motor control system having a timer processor which generates multiple synchronized PWM waveforms while minimizing software latency effects. The timer processor generates a 50% PWM duty cycle sync signal at the PWM frequency, creating a logic level transition (leading edge) in each PWM period. At each such transition, the timer processor interrupts the host processor for the purpose of updating a multi-byte timer data register with PWM on-time data stored in nonvolatile memory as a function of machine position and requested current. A separate timer channel is provided for each PWM waveform to be generated, and the timer processor sets off-to-on and on-to-off transitions of each waveform in accordance with the updated PWM on-time data such that respective off-to-on and on-to-off transitions in each waveform are centered about the leading edges of the sync signal.