Abstract: A technique for reducing latencies in bridge operation, by facilitating cut-through transmission of a receive data packet while the packet is still being received, but without the need for starting or ending delimiters,or packet lengths, in the packet data. The technique can be applied to packets inbound from a network, packets outbound to a network, or packets being looped back to a client to which the bridge is connected. In the technique of the invention, each received packet is stored in a buffer memory and a count is maintained of the number of bits in the received packet. A transmit operation is started as soon as possible, preferably while the packet is still being received, and bytes are retrieved from the buffer memory for transmission. The transmit operation is terminated when a transmit byte count reaches the packet length as determined by the receive byte count.

Abstract: A magnetic tape recording system which achieves very high track densities through utilization of a recording method and apparatus. A magnetic head is described in which the read head gaps are parallel to but laterally offset from the write head gaps. A head assembly is further provided in which the magnetic head is mounted on a rotary motor for aligning the head for writing and reading tracks at different azimuth angles, as well as a stepping motor and linear actuator for stepping the head between tracks. Also, a servo tracking method and apparatus is presented in which writing and reading take place under servo control. This servo allows alignment of the write head gap during writing, and the read head gap during reading, through observation of low frequency servo data blocks dynamically imbedded amidst adjacent track data. The utilization of this servo minimizes tracking error due to lateral tape motion.

Abstract: A node operating in a network using the International Standard Organization (ISO) High-Level Data Link Control (HDLC) network protocol includes a mechanism for encoding information such that frames including the encoded information can be correctly interpreted by nodes operating in either of the standard 16-bit or 32-bit ISO-HDLC operating modes. The encoding mechanism produces a preliminary frame check sequence by encoding the information in an encoder using a generator polynomial G.sub.48 (x), which is a combination of the generator polynomials G.sub.16 (x) and G.sub.32 (x) which are used to produce frame check sequences for nodes operating in 16-bit or 32-bit modes, respectively. Before the information is encoded, the encoding mechanism sets the encoder to an initial condition using an initializing polynomial I.sub.48 (x). The preliminary frame check sequence is further encoded by adding to it a complementing polynomial C.sub.48 (x). The result is a 48-bit frame check sequence.

Abstract: A simulation method allowing an experimenter to model a real-world situation in order to learn something about it. The method permits interaction of concurrent experiments through interaction between different variables during a single simulation run on a computer having at least one central processing unit.

Abstract: A computer program of complex instruction set code (CISC) is translated to produce a program of reduced instruction set code (RISC). Each CISC instruction is translated into a sequence of RISC instructions. The sequence includes in order four groups of instructions. The first group includes instructions that get inputs and place them in temporary storage. The second group includes instructions that operate on the inputs and place results in temporary storage. The third group includes instructions that update memory or register state and are subject to possible exceptions. The fourth group includes instructions that update memory or register state and are free of possible exceptions. When execution of the RISC program is interrupted by an asynchronous event, the RISC instruction being executed at the time of the interrupt is recorded and allowed to complete.

Abstract: The invention relates to a switching power supply having a protection device to shutdown the supply of the output voltage and a circuit for providing a trickle voltage while the power supply is shutdown. The power supply is shutdown by lowering the primary bias voltage, the voltage which powers the internal components of the power supply, to a value which disables the production of the output voltage. However, the primary bias voltage is not reduced to ground. Various circuits and devices, such as a restart circuit, may then be powered by the trickle voltage while the power supply is shutdown.

Abstract: A method and apparatus for optimizing the track seeking operation of disc drives by adaptively changing the seek velocity profile in response to the actual performance of the drive during track seeking operations based upon the amount of head overshoot and the actuator power dissipation.

Abstract: There is provided a method and materials for cooling the power train components, such as transformers, rectifiers, chokes, and the like, of an integrated on-board power supply IOP) using a single heatsink. Spacers are positioned between the power train components and a substrate, the substrate for mounting the components. The spacers are individually dimensioned and shaped to raise the heat-removal surfaces of the components to a substantially uniform and minimal height. A heatsink having a substantially planar, heat-acquiring surface is positioned on the heat-removal surfaces of the power train components. Fasteners are used to compress the spacers, urging the components against the heatsink to provide a substantially continuous and coplanar thermal interface between the components and the heatsink. After the components, heat sink and substrate have been fastened to each other, the components are electrically connected to the substrate by soldering.

Abstract: An apparatus is disclosed for fluid dynamically augmenting a heat sink to displace a boundary layer in the cooling fluid adjacent to the surfaces of the heat sink cooling fins. Ribs with a thickness slightly less than the thickness of the boundary layer cause secondary flow in the cooling fluid downstream from the rib in the form of vortices which displace hotter slower moving fluid by drawing in cooler fluid farther from the surface of the fins. The ribs are constructed on the surface of the cooling fins in an inverted V-shaped configuration. The angle of the ribs in the inverted V-shaped configuration is optimized to intersect the entire flow of the fluid through the heat sink forming a means for efficient dissipating heat from the heat sink over its entire surface area.

Abstract: A technique for establishing and maintaining full duplex communication between two stations connected to a token ring network, without physically reconfiguring the station connections or otherwise disturbing the network. In an auto-configuration full duplex mode of operation, each station ascertains whether there are only two active stations on the network and, if so, performs an exchange of frames with the other station to establish full duplex communication. One way to ascertain whether only two stations are active is for each station to transmit periodically a neighbor information frame, which contains the identities of the source station and the source station's nearest upstream neighbor. Once established, full duplex communication can proceed at a greater bandwidth than communication in a token ring network, and without latency delays and distance limitations associated with token ring networks.

Abstract: A message switching network is disclosed which consists of end units between which messages flow. The end units are coupled together directly (via LANs) or via common switching nodes through level 0 links; the nodes are coupled together via level 1 links; and the nodes are grouped into areas which are coupled together via level 2 links. A message entering a node has its destination area code compared with the node's area code, and an area/port table or an end unit/port table is used to look up the output port which is coupled to the end unit, next node in the area, or next area to which that message is to be delivered. Logic circuitry determines the incoming and outgoing levels, and a transition between levels is logged together with certain details of the message. Messages are thus monitored--i.e., their passage is recorded--when they cross levels in the hierarchy.

Abstract: An apparatus is disclosed for testing the immunity of an electronic device to interfering electromagnetic radiation. The apparatus includes a room enclosing a bounded space for containing the electronic device to be tested and a plurality of radiating elements disposed on the interior surfaces of the room for generating an electromagnetic field in the room. Each of the radiating elements includes a controllable phase shifter, a controllable amplifier, and antenna. The circuits of the phase shifter and amplifier are connected by a common signal bus to a radio-frequency signal source and by a common control bus to a controller for individually adjusting the phase and amplitude of the radiated signal to create an electromagnetic field within the room having a predetermined strength and distribution.

Abstract: A compiled, rule-based expert system for a data base. The system incorporates compiled declarations to incorporate the concept of strong typing at compile time. Both data and rules can be declared so as to be accessible from one or more modules, as required. Such a scheme reduces program complexity, reduces program development time, and increases the ease with which rule-based programs may be embedded in procedural programs.

Abstract: A plug-in logic board for use in an arbitration mechanism is disclosed. The disclosed arbitration mechanism includes two or more request processing units, two or more grant processing units and a common broadcast medium. The request processing units and the grant processing units use the common broadcast medium to control the coupling between requesters and resources on a first come, first served basis. The disclosed logic board includes a request processing unit coupled to the common broadcast medium, a grant processing unit coupled to the common broadcast medium, and an input/output unit coupled to an electronic operating device. The input/output unit passes a resource type request signal from the electronic operating device to the request processing unit, and passes a status signal received from the electronic operating device to the grant processing unit. The input/output unit further outputs a grant signal received from the request processing unit to the electronic operating device.

Abstract: A method and apparatus for transferring packets of information with different attributes from a device interface to buffers in a host memory dedicated to particular attribute values or ranges of values. The apparatus consists of multiple shared data structures in the form of receive rings, each associated with memory buffers dedicated to a particular range of values for a particular packet attribute. The device interface determines which receive ring is associated with a buffer dedicated to the proper attribute value range by comparing the value of the attribute of the received packet with the values of attributes associated with the buffers of each ring. A sequencing ring is provided to store the order in which each receive ring must be accessed by the host cpu when retrieving packets. This sequencing ring ensures that the host cpu will retrieve the packets in the order in which they were received.

Abstract: A method and arrangement for preventing the locking out of devices which are coupled to a bus by either of two of the devices which have become initiator and target devices respectively. The devices arbitrate for control of the bus after the bus enters a bus free phase. The device which wins the arbitration becomes an initiator. A timer in each device on the bus is started upon the initiation of the arbitration. The initiator device is removed from the bus when an elasped time after the timers have been started reaches a pre-determined value. The distributed clock of the invention ensures that the devices coupled to the bus will clear the bus after the initiator has been on the bus for a pre-determined time, thereby obviating skew problems associated with single clocked systems.

Abstract: An improved method for linking images at program activation is provided by use of a symbol vector in a sharable code image. The symbol vector is automatically constructed which the linker and operating system use to effect fast lookup of symbol values at program activation, thus providing flexibility similar to that of link-time binding. For each sharable image being constructed, the programmer provides a list of symbols which are to be made visible outside of the image. These symbols may be procedure names, data cells, absolute values, or any other valid use of a symbolic value. The order of this list must remain fixed from one image build to the next. From this list, the "symbol vector" is constructed (as by the linker) of the value of each of the identified symbols, and the symbol vector is associated with the sharable image. A symbol table is also associated with the sharable image, where each symbol has the value of its index in the symbol vector.

Abstract: An computer assembly having an integral video display and processor subsystem in a single enclosure is described. The assembly contains an electrically conductive safety wall inside the enclosure which separates the interior of the enclosure into a high-voltage region where the video display components are mounted, and a low-voltage region where the processor subsystem is mounted. The enclosure has a removable rear cover which allows access to the processor subsystem for upgrading memory. An electrically conductive liner is attached to the rear cover for EMI shielding of the low-voltage region.

Abstract: A network adapter with high throughput data transfer circuit to optimize network data transfers, with host receive ring resource monitoring and reporting is disclosed. Time critical network data is transferred between the network adapter and the host computer system by means of a high throughput data transfer circuit. The high throughput data transfer circuit is designed to provide throughput equal to the bandwidth of a high speed local area network such as the Fiber Distributed Data Interconnect. The high throughput data transfer circuit will inform the local intelligence of the network adapter if the network adapter has used up all host computer system memory allocated for storing data received from the network. Adapter management data is transferred between the network adapter and the host computer system local area network through a lower throughput data transfer circuit.

Abstract: A simulation method allowing an experimenter to test and debug computer programs concurrently. The method ultilizes the generation of signatures to observe interactions of various subprogram paths with a reference case.