Abstract: A circuit employable as a differential multiplexer (10, 310, or 610) or as a differential logic gate (110, 210, 250, 410, or 510) of either the OR/NOR or EXCLUSIVE OR/EXCLUSIVE NOR type contains four pass gates that operate on four circuit input signals and are controlled by two additional circuit input signals. Two of the pass gates drive a bipolar transistor serially coupled to a first FET driven from the other two pass gates. Likewise, the second pair of pass gates drive another bipolar transistor serially coupled to another FET driven from the first pair of pass gates. The bipolar transistors supply respective circuit output signals. The two FETs are of a first polarity. The circuit preferably includes a pair of FETs of a second polarity opposite to the first polarity. The second pair of FETs are arranged so as to provide output pull-up/pull-down assistance for the bipolar transistors.

Abstract: The driver circuit comprises drive means (Q2) for drawing an output current from a bus line (13) in a first state of the circuit. An output diode (S1) in the path of the output current is reverse biased in a second state of the circuit to isolate the drive means from the bus line. A control current (I.sub.Q2B) for the drive transistor is drawn from the bus line (13), beyond the output diode (S1). By this means, power dissipation (heat) within the driver circuit due to the control current is eliminated. The driver circuit also comprises means (26, S3, P1) for biasing the output during connection of the circuit to a live bus line, so as to reduce noise for other circuits connected to the bus line.

Abstract: In a memory element comprising interconnected logic gates with field effect transistors metastable states are to be avoided. The device's immunity against staying in metastable states is considerably raised by coupling a supply terminal of each logic gate to a power supply voltage via a base-emitter path of a bipolar transistor that has its collector coupled to the logic gate's output.

Abstract: The tail current of a differential transistor pair (12 and 14) is controlled by a feed-back means (40) that couples the pair's tail node (16) to the control input of each transistor for controlling a biasing current through each transistor. The control input of each transistor further receives an input signal in addition to an output signal of the feed-back means. As a result, the circuit has a stable and accurate tail current, and in addition is suitable for a low-voltage supply or for high-current operation.

Abstract: A reduced-temperature two-step silicon deposition performed at different silicon sources is used in forming a composite monosilicon/polysilicon layer (20/24/26) on a body that contains a monosilicon region (10) and an adjoining dielectric regin (12). The first step entails selectively depositing silicon, preferably using dichlorosilane as a CVD silicon source, to grow a first monosilicon layer (20) on exposed monosilicon at an average body temperature less than or equal to 950.degree. C. Substantially no silicon accumulates on exposed dielectric material during the first step. The second step entails non-selectively depositing silicon, preferably using silane as a CVD silicon source, at an average body temperature less than or equal to 950.degree. C. to grow a second monosilicon layer (24) on the first monosilicon layer and to simultaneously grow a polysilicon layer (26) on the exposed dielectric material.

Abstract: Electrical connections to specified semiconductor or electrically conductive portions (18, 26, and 30) of a structure created from a semiconductive body (10) are created by a process in which a titanium contact layer (34) is deposited on the structure over the specified portions. An electrically conductive barrier material layer (36) which consists principally of non-titanium refractory material is formed over the contact layer. The resulting structure is then annealed at a temperature above 550.degree. C. in order to lower the contact resistance. The anneal is preferably done at 600.degree. C. or more for 10-120 seconds in a gas whose principal constituent is nitrogen. An electrically conductive primary interconnect layer is formed over the barrier material layer after which all three layers are patterned to create a composite interconnect layer.

Abstract: An optical record carrier having an information track structure on a surface thereof, one or more of the tracks being pre-recorded with standard information pertaining to a particular class of information of common use to an undefined number of users. Portions of one or more tracks which are not so pre-recorded are covered with a layer of optically recordable material, for recording thereon of information of the aforesaid class which completes or updates the standard information in whole or in part.

Abstract: A circuit formed with an input stage (20) and an output stage (22 or 28) uses capacitively enhanced switching to improve switching speed without significantly raising steady-state current utilization. The output stage contains a pair of amplifiers (A1and A2) that respond to complementary signals (V.sub.M1 and V.sub.M2) produced by the input stage. The amplifiers are coupled to a pair of corresponding nodes (N1 and N2). A third amplifier (A3) in the output stage has a control electrode coupled to one of the nodes, a flow electrode coupled to the other node, and another flow electrode coupled to a further node (N3). A current supply (24) provides current at the further node. A charge/discharge element (CD1) produces a capacitive-type charge/discharge action between the further node and a source of a reference voltage (V.sub.R1).

Abstract: A monolithic integrated circuit contains a field-programmable logic architecture centered on a single array of programmable gates that perform either logical NAND or logical NOR operations. Foldback loops can be readily programmed through the array to enable the user to achieve different numbers of logic levels.

Abstract: A record carrier for information, for example video and/or audio information, in the form of a disk-shaped carrier substrate provided with an optical structure in accordance with the information is described. By making the optical structure radiation-reflecting and the substrate radiation-transmitting, while the surface of the substrate more remote from the optical structure forms both the entrance face and the exit face for the read radiation, and by coating a surface of the optical structure more remote from the substrate with an additional layer, a simple record carrier is obtained which is well protected against dust particles and damage.

Abstract: A planar electrical interconnection system suitable for an integrated circuit is created by a process in which an insulating layer (31) having a planar upper surface is formed on a substructure after which openings (32) are etched through the insulating layer. A conductive planarizing layer (33) having a planar upper surface is formed on the insulating layer and in the openings by an operation involving isotropic deposition of a material, preferably tungsten, to create at least a portion of the planarizing layer extending from its upper surface partway into the openings. The planarizing layer is then etched down to the insulating layer. Consequently, its upper surface is coplanar with that of the material (33') in the openings. The foregoing steps are repeated to create another coplanar conductive/insulating layer (34 and 36'). If the lower openings are vias while the upper openings are grooves, the result is a planar interconnect level. Further planar interconnect levels can be formed in the same way.

Abstract: In hermetically sealing a base structure (10) of a ceramic package for a semiconductor device to a cap structure (12) of the device, one or more venting slots (36) are initially provided in the base sealing layer (16) or in the cap sealing layer (26). The base and cap structures are then fused together along the two sealing layers and electrical leads (20) by bringing the structures into contact and heating them to a temperature high enough to cause the sealing material to flow readily. The venting slots allow air to escape during the fusing step. This inhibits the formation of air bubbles along the sealing interface and thereby improves the hermeticity of the seal. The structures are subsequently cooled to harden the sealing layers into a unitary layer (28).

Abstract: An integrated circuit (10, 22) contains an active bypass (36) that inhibits high-frequency supply-voltage variations caused by interaction of the circuitry elements (28) with the parasitic inductances (L.sub.HE, L.sub.HP, L.sub.LP, and L.sub.LE) associated with the power supply lines (16.sub.H /24.sub.H /26.sub.H /32.sub.H and 16.sub.L /24.sub.L /26.sub.L /32.sub.L) for the circuit. The bypass centers around a transistor (Q.sub.BP) coupled between the supply lines. An activation circuit (38) provides the transistor with a control signal (V.sub.C) to activate the transistor. A sensing capacitor (C.sub.S) provides a capacitive action between the transistor control electrode and one of the supply lines.

Abstract: A semiconductor device contains a stress-relief layer (46) having a glass transition temperature of 25.degree. C. or less. The layer generally lies above an electrical interconnection system (12) in the device but does not overlie bond pad areas. This substantially alleviates thermally induced stress that could otherwise damage electronic components in the device while simultaneously allowing the maximum stress on electrical conductors (32 and 34) that protrude from the external package coating (48) to occur at bonding areas which can tolerate the stress. The layer preferably is a silicone polymer consisting of exposed photosensitive material.

Abstract: An optical information recording and/or read system comprises an optically readable record carrier (1) and an optical read and/or recording apparatus (FIG. 2). The record carrier (1) is provided with substantially concentric tracks (2). The record carrier (1) is divided into sectors (4). In the tracks of each sector address information is recorded by means of prior recorded radially juxtaposed address information patterns (8). The read and/or recording apparatus (FIG. 2) comprises a driver (20, 21) for rotating the record carrier (1), scanner (23, 25) for scanning the tracks (3) with a radiation beam (2) for the purpose of recording and/or reading, a closed-loop tracking system (23, 26) for keeping the radiation beam (24) aimed at the track (6) to be scanned, and an angular-position-detection system (23, 26, 27) for determining the angular position of the record carrier (1).

Abstract: An ISL clamped NPN transistor and a PNP interface transistor are merged together in a single semiconductive isolation island. The two transistors are laterally separated from each other along a semiconductive surface of the island, which also includes one or more metallic elements forming individual Schottky barrier contact diodes with the semiconductive surface. The PNP transistor provides translation between an ISL logic gate and a TTL logic gate. One of the Schottky diodes may be used in combination with the NPN transistor as an active pulldown for an output transistor of the TTL logic gate.

Abstract: A method of fabricating a CMOS-type structure entails forming a pair of conductive portions (68 and 70) on a pair of dielectric portions (72 and 74) lying on monocrystalline silicon (60). N-type dopant-containing ions are implanted into the silicon to form a pair of doped regions (78/82) separated by p-type material under one of the dielectric portions. Boron dopant-containing ions are similarly implanted to form a pair of doped regions (84) separated by n-type material under the other dielectric portion. A sacrificial oxidation is performed by oxidizing surface material of each conductive portion and each doped region and then removing at least part of the so oxidized material (86) down to the underlying silicon. Tungsten (88 and 90) is deposited on the exposed silicon after which a patterned electrical conductor is provided over the tungsten. Use of the sacrificial oxidation substantially reduces tunnel formation during the tungsten deposition.

Abstract: The size of a fusible link (22C.sub.F) created from part of a metal layer (22) is controlled by an oxidation performed in a deposition chamber that is also used for depositing a dielectric layer (30) over the fuse structure. The metal layer serves as a diffusion barrier between semiconductor material (14 and 16) and another metal layer (24).

Abstract: Apparatus and methods for remodulating digital luminance and color difference components for display as PIP information, or together with other composite video components for multi-PIP and test pattern applications are disclosed. A digital encoder is used for conducting a digital quadrature modulation on the color difference components and for digitally adding the luminance signal thereto prior to the converting of the remodulated information into an analog format. Preferably, the digital video information output by the encoder is in the form Y1+(R-Y)1, Y1 +(B-Y)1, Y2-(R-Y)1, Y2-(B-Y)1, Y3+(R-Y)2. Y3+(b-Y)2, Y4 -(R-Y)2, . . . , where Y is the luminance component, R-Y and B-Y are color difference components, and where the numbers index received samples of the video components with the luminance component being sampled at twice the frequency of the color difference components.

Abstract: In a transistor fabrication process, the use of a three-step base doping technique enables the characteristics of a vertical bipolar transistor to be controllably reproduced at highly optimal values from run to run. Insulating spacers (52A) are employed in forming a self-aligned base contact zone (58B). A shallow emitter (46) is created by outdiffusion from a patterned non-monocrystalline semiconductor layer (38A) that serves as the emitter contact. The fabrication process is compatible with the largely simultaneous manufacture of an insulated-gate field-effect transistor of the lightly doped drain type.