Abstract: A method for locating a carrier (220) includes the steps of tuning to a first anticipated carrier location (240) within a first subband division (216), attempting to locate the carrier (220) at the first anticipated carrier location (240) within the first subband division (216), tuning to a second anticipated carrier location (223) within a second subband division (217) if failing to locate the carrier in the first subband division (216), and attempting to locate the carrier (220) at the second anticipated carrier location (223) within the second subband divisions (217).

Abstract: A data link control method including receiving a message (30) for transmission over a cable communications system. The method determines a number of octets in the message (30). When the number of octets is less than or equal to a predetermined number of octets, the method sets a frame length (44) equal to the number of octets and transmits a frame (180) containing the message (30). When the number of octets is greater than the predetermined number, the messages (30) is segmented (32-42), each segment being identified in order with respect to the other segments. The method thereby provides for graceful communications resumption when the transmission of a message is interrupted before completion.

Abstract: A control unit (102) efficiently decodes burst signal transmissions in a TDMA-based telecommunication system (100) by decimating down the number of samples requiring processing during symbol detection. The control unit (102) includes a sampling receiver (304) that inputs burst signals from cable access units, converts them to a pair of baseband quadrature signals, I and Q. The sampling receiver (304) also includes an A/D converter (314) that samples the I and Q signals at preferably four times the symbol rate. A digital signal processor circuit (306) produces a timing error signal for substantially all of the samples. The digital processor circuit (306) also accumulates a timing error sum for each of the four samples. The processor circuit (306) selects the optimum sample as the sample between the samples having the largest positive and negative error sums. The processor circuit (306) also includes a .pi./4-DQPSK differential detector that processes the optimum sample of each symbol for symbol detection.

Abstract: Carriers (51) in a communication system (10) are prioritized (70) according to their usability. The carriers (51) that are below a usability threshold are placed on an ingress list (122). Those that exceed the threshold are placed on a preferred list (121). The carriers (51) on the preferred list (121) are then ranked (76) according to their word error rates (WER) and signal quality (SQ). The carriers (51) on the ingress list (122) have their usability re-checked periodically and may be transferred to the preferred list (121) if their usability does not again drop below threshold during a pre-set time period.

Abstract: A method and apparatus attach a connector (17) to an edge (32) of a substrate (18) such that an electrical connection is formed between the circuits on the substrate (18) and the leads (12, 14) on the connector (17). A connector (17) is provided having leads arranged into a top row (12) and a bottom row (14) extending horizontally therefrom. A substrate (18) is provided having a row of solder bumps (20) on a bottom side to correspond with the bottom row of leads (14) of the connector (17) and a row of solder paste pads (22) on a top side to correspond with the top row of leads (12) of the connector (17). The edge (32) of the substrate (18) is approached with the connector (17) at an angle, straddling the edge (32) with the top row (12) and the bottom row (14) of leads, and rotating the connector (17) into parallel alignment with the substrate (18).

Abstract: A semiconductor material contacting member which greatly reduces potential for semiconductor material breakage is provided. Preferably, the contacting member is a ceramic cylinder (60) which can be used to brace a semiconductor wafer (14) in a wafer station (2) of a sputtering system. The ceramic cylinder has an annular shoulder at one end (68), with a flat outer surface. The flat outer surface contacts the wafer (14) along a line (74). The line contacting surface (74) distributes pressure and heat across the contacting surface. Additionally, the ceramic cylinder (60) is relatively soft, thus avoiding damaging the semiconductor material.

Abstract: A method for making a substrate structure with improved heat dissipation is provided. A semiconductor wafer (14) is provided. A diamond layer (12) is formed on the back (20) of the wafer (14). The diamond layer (12) provides structural support and heat dissipation. In certain embodiments, the diamond layer may be an amorphous diamond substrate ( 12 ) bonded to the semiconductor wafer (14), In certain other embodiments the diamond layer (12) may be a thin film layer (12) deposited on the back of the semiconductor wafer (14). The semiconductor wafer (14) is thinned to a minimum thickness necessary for forming an electronic device in a surface (22) of the wafer (14).

Abstract: A semiconductor structure that provides both N-type and P-type doping from a single dopant source is provided. A first doping region (13) comprising a first material composition includes holes and electrons in a doping energy level (E.sub.D)- A first undoped spacer region (12) comprising the first material composition covers the doping region (13). An undoped channel (11,14) comprising a second material composition covers the first spacer region (12) and a second undoped spacer region (12) comprising the first material composition covers the undoped channel (11,14). The first material composition has a wider bandgap than the second material composition and the doping energy level (E.sub.D) is selected to provide electrons to the undoped channel (11,14) when the second material composition has a conduction band minimum less than the doping energy level (E.sub.

Abstract: A semiconductor structure that provides intrinsic doping from native defects is provided. A quantum well including a narrow bandgap material (11, 14) having a low concentration of native defects is sandwiched between two wide bandgap spacer layers (12, 20, 17, 15). The spacer layers (12, 20, 17, 15) have a low concentration of native defects. At least one doping region (13, 16) having a high concentration of native defects positioned adjacent to one of the undoped spacer layers (12, 17).

Abstract: A quantum well structure having a host optical phonon confinement well (11) having a characteristic phonon distribution (16), and at least one charge carrier confinement well (17) located near a minima of the phonon distribution (16). In one embodiment, a wide bandgap layer (13) is formed in a central portion of the host optical phonon confinement well (11), wherein the wide bandgap layer (13) has phonon properties closely matching that of the host phonon confinement well (11).

Abstract: A semiconductor device having a vertical interconnect or via stacked formed by quantum well comprising a semiconductor material is provided. A first semiconductor device (11) having a current carrying region (19) is formed in a first horizontal plane. A second semiconductor device (12) having a current carrying region (29) is formed in a second horizontal plane. Each of the current carrying regions have a first quantized energy level that is substantially equal. A semiconductor via (31) couples the current carrying region (19) of the first semiconductor device (11) to the current carrying region (29) of the second device (12), wherein the semiconductor via (31) has a first quantized energy level capable of alignment with the quantized energy levels of the current carrying regions (19, 29) of the first and second semiconductor devices (11,12).

Abstract: A semiconductor device having a lateral interconnect or via formed by quantum well comprising a semiconductor material is provided. The lateral interconnect (17, 18, 19) formed by a quantum well comprising a first semiconductor material composition. A first semiconductor region (11, 12, 13) comprising a second material type is formed adjacent to the lateral interconnect (17, 18, 19). A second semiconductor region (23, 24, 26) comprising the second material type is adjacent to the lateral interconnect (17, 18, 19) so that the lateral interconnect (17, 18, 19) separates the first (11, 12, 13) and second (23, 24, 26) semiconductor regions. The first (17, 18, 19) and second (23, 24, 26) semiconductor regions have a first quantized energy level that is substantially equal. The lateral interconnect (17, 18, 19) has a first quantized energy level capable of alignment with the quantized energy levels of the first (11, 12, 13) and second (23, 24, 26) semiconductor regions.