Abstract: A process of manufacturing a semiconductor device including a buried channel field effect transistor comprising, for realizing said field effect transistor, steps of forming a stacked arrangement of semiconductor layers on a substrate including an active layer (3), forming a recess in said active layer, referred to as gate recess (A4), for constituting a channel between source and drain electrodes, and forming a submicronic gate electrode (G) which is in contact with the active layer (3) in said gate recess (A4), wherein: the gate recess width (Wri) and the gate length (LGo) are manufactured with predetermined respective values, in order that the access region, defined between the gate (G) and the gate recess edge (31), has an access region width (2&Dgr;o), derived from said predetermined values (Wri, LGo), which is sufficiently small to permit the transistor of functioning according to saturation current characteristics having continuous slopes.

Abstract: To provide a circuit arrangement for protecting the input of an integrated circuit particularly suitable for analog signals, more specifically a CMOS circuit, against overvoltages, said circuit arrangement (100) comprising: at least two input terminals (10; 20) and at least one protection stage (S) in which each input terminal (10; 20) is connected to a power supply voltage (US) by a respective protection diode (12; 22), particularly a semiconductor diode, and to a reference potential (UR) by a respective protection diode (16; 26), particularly a semiconductor diode, by which, on the one hand, disturbing demodulation effects affecting the signal path can be reliably avoided in the input signal due to a simple and low-cost structure, and, on the other hand, effective protection of overvoltages caused by electrostatic discharges is ensured, it is proposed that at least a further diode (14, 18; 24; 28) is arranged in series with each protection diode (12, 16; 22, 26), and the protection stage (S) precedes at