Abstract: Systems and methods for determining offset phasors are disclosed. An offset vector is computed from a current channel impulse response and a previous channel impulse response. A first vector and a second vector are simultaneously and iteratively rotated in opposite directions to determine an offset phasor. A first vector of the pair of vectors is initialized with a constant value for its x coordinate and a zero for its y coordinate. A second vector of the pair of vectors is initialized with the x and y coordinates of the offset vector. The vectors are rotated in opposite directions using shift operations for a specific number of iterations. After the final rotation, the y coordinate of the second vector has become zero and the x and y coordinates of the first vector correspond to the sine and cosine of the angle formed by the offset vector. The cosine and sine terms form the real and imaginary parts of the offset phasor.

Abstract: A DSL modem (50). The DSL modem includes a connector (62) comprising a first pair of conductors (IP1, IP2) and a second pair of conductors (OP1, OP2). The DSL modem further includes both circuitry for transmitting according to a DSL protocol (52) and circuitry for receiving according to a DSL protocol (52). Still further, the DSL modem includes switching circuitry (60) operable to selectively switch to a first position to couple the circuitry for transmitting and the circuitry for receiving to the first pair of conductors and to a second position to couple the circuitry for transmitting and the circuitry for receiving to the second pair of conductors. Lastly, the DSL modem includes circuitry (52, CONTROL) for controlling the switching circuitry to switch to one of the first position and the second position and for then detecting whether DSL service exists along the pair of conductors to which the circuitry for transmitting and the circuitry for receiving is then coupled.

Abstract: A subscriber line interface circuit is provided that posses an output impedance that may be greater than about 2.2 Kohms at at least some frequencies associated ADSL communications. In at least some embodiments, such ADSL frequencies include frequencies greater than about 30 KHz. In some embodiments, the subscriber line interface circuit includes an output driver that provides voice signals on a telephone line on which digital data is also provided by a data driver and a filter coupled to the output driver wherein the output impedance of the subscriber line interface circuit is greater than about 2.2 Kohms at at least some frequencies greater than 30 KHz.

Abstract: A pipeline ADC implemented with both general charge redistribution stages and flip-around charge redistribution stages. Using the flip-around charge redistribution stages leads to reduced power/area consumption, but could lead to accumulation and propagation of errors. general charge redistribution stages are used to control/contain the errors. As a result, the ADC is implemented to achieve an acceptable bit error and power efficiency combination. According to another aspect of the present invention, the first stage is implemented as a flip-around charge redistribution stage (in combination with general charge redistribution stages in subsequent stages) since there is no accumulation of error from prior stages, and implementing the first stage as a flip-around charge redistribution stage gives maximum advantages in power efficiency.

Abstract: A method of optimally distributing signal power for multiple users over a xDSL or wireless channel considers uses computationally efficient tools to achieve improved crosstalk avoidance. The method chooses between EQPSD and FDS signaling in a fashion that maximizes overall data rate. Rather than choosing EQPSD signaling in regions where there is low self-NEXT, but where the echo is high (relative to signal power), the method selects FDS signaling since the communication system acts in a manner similar to self-NEXT in such regions.

Abstract: A method 10 is provided to mitigate DC offset in a sign bit correlator associated with a packet detection circuit. The input sign pattern is monitored; and if a long run of the same sign is seen, a sign bit is replaced with a bit generated using a desired pseudorandom noise (PN) sequence. This ensures that the correlator only reacts substantially to correlations that are not due to DC offset.

Abstract: A method of converging a step size control for an adaptive filter of a communication channel including: (1) initializing a nominal step size value and a penalty point value; (2) combining the nominal step size value and the penalty point value to generate a step size value; and (3) dynamically changing the step size value in response to a characteristic measure of a quality of the communication channel. The step size value is changed by adjusting the nominal step size value, the penalty point value, or both. In a preferred embodiment the penalty point value is adjusted dependant on: (1) a tone originating from the far end (2) full convergence (3) the power level of a residual error signal (4) the channel's near-end background noise and/or (5) weak double-talk in the communication channel. The nominal step size value is adjusted when an achieved initial combined loss is about 15 dB or greater and is reset by divergence.

Abstract: System and method for a multi-standard sigma-delta modulator. A preferred embodiment comprises an integrator coupled to a signal input, wherein the integrator is configured to sum a difference between an input signal and an output of the sigma-delta modulator. A dithering circuit, also coupled to the signal input, is used to produce a dithering sequence. A summing point combines an output of the integrator and the dithering circuit while a quantizer converts the combined outputs into one of several discrete levels. The sigma-delta modulator further comprises a reset circuit to reset the sigma-delta modulator if the integrator becomes saturated. The sigma-delta modulator, as described, is compatible with G.Lite, ADSL, and ADSL+ variants of the digital subscriber line technical standards.

Abstract: A receiver architecture featuring a decimation filter and a bypass around said decimation filter is disclosed along with a method for optimizing said receiver's sampling phase and programmable gain amplifier. Said method utilizes said receiver architecture to modify said receiver's receive path to simplify optimizations.

Abstract: A method and apparatus for accurately estimating the carrier frequency offset and the carrier phase offset of a digitally modulated signal using a signal processing algorithm to initialize the state variables of a Phase-Locked Loop (PLL) is disclosed. A sequence of phase values is estimated from a received sequence of symbols and the angular effect due to the modulation format is removed from the sequence of phase values. A curve-fit algorithm based in one embodiment on the RLS algorithm is then applied to a sequence of unwrapped phase values to estimate the carrier frequency offset and the carrier phase offset.

Abstract: The roaming of a wireless device 115 extends the effective range of a wireless network 100 by passing a device 115 between access points as the device leaves the coverage area of one and enters another. Roaming can be slow and problematic if an old link is disconnected prior to establishing a new link, especially if authentication and security is required. The present invention speeds up roaming by using existing mechanisms to initiate a new link with a new access point 120 prior to disconnecting the old link with an old access point 110.

Abstract: The present invention provides an apparatus, system and method for synchronizing a local clock signal with a remote clock signal in a communication network. Phase information is used to calculate a number of “clock jitters” per unit of time needed to synchronize the locally generated clock with the remote clock. Introducing (removing) a given amount of delay at a particular point in the local clock signal results in a positive (negative) jitter in which its minimum value defines the jitter resolution. The jitters are introduced to the local clock signal from a plurality of tapped delay line elements (310) selected by a phase selector (350) in response to a timing correction signal issued by a phase error module (520).

Abstract: A method for embedding a Joint Test Action Group (JTAG) standard IEEE 1149.1 host controller into a field programmable gate array (FPGA) for platform development and DSP programming, and boundary scan of targeted hardware using JTAG commands and architecture is described. The FPGA-based JTAG host controller is bussed directly into the FPGA core, bypassing the board's JTAG communication port.

Abstract: A launch multiplexor which enables a desired bit to be stored into a desired memory element when using sequential scanning techniques (e.g., automatic test pattern generation (ATPG)). The launch multiplexor may be employed in addition to a scan multiplexor, which enables the test pattern bits or normal operating input to be selected and stored in the desired memory element. The scan multiplexor is used to scan-in a test pattern and evaluate a first input, and the launch multiplexor provides the control to store a desired bit into the corresponding memory element. Another output may be evaluated after storing the desired bit. In an embodiment, launch multiplexors are used associated with only memory elements in the critical paths, and the delay in transitioning from one output to another may be conveniently measured.

Abstract: A dithering method is provided for sigma-delta converters in a deep-submicron process. The dither is a random interleaving of quantizer thresholds levels. The random interleaving dither is more effective than previous static dither methods to remove idle channel tones of sigma-delta analog-to-digital converters (ADC). The dither is easy to implement and takes less area than other dynamic dither methods.

Abstract: An echo canceller, which includes, receives and sends paths connected to standard telecommunication interfaces, a non adaptive filter with filter reflection coefficients which generate an estimated echo signal, which when subtracted from the send path input produces a nearly echo free send path output, an adaptive filter generating a second estimated echo signal, which when subtracted from the send signal, provides a possible alternative nearly echo free send path signal, a fast non iterative least squares method of estimating a reflection, a controller means which, in response to an observed non echo free send path output, causes the fast non iterative least squares method to search for possible new reflections, and a controller means for expurgating unnecessary reflection coefficients in the non adaptive filter.

Abstract: Modem relay provides a local interface to the modem on both ends of a call, demodulates the full duplex data stream, packetizes the bits for transport over an IP network, and remodulates the data stream at the remote end. It is advantageous to measure the throughput efficiency of the modem relay. The modem relay provides bandwidth savings, and resistance to network packet loss. However, the resistence is often accomplished by redundancy techniques which can reduce effective throughput rates. Because the modem data stream can be transported in a redundant fashion, which allows for seamless error recovery in the event of single or double packet loss events, lost packet recovery minimizes computational requirements and provides for recovery of lost packets during burst loss of a series of sequential packets. The present invention teaches a system and method for determining the throughput of various modem relay implementations.

Abstract: An apparatus and method for improving data transfers between a network and a network device is provided. The apparatus comprising a data input, a programmable counter adapted to counting the number of data packets received, an interrupt generator for signaling a microprocessor upon a signal from said programmable counter, a data processing block for examining the contents of data packets for an end-of-packet flag, and an output.

Abstract: A system and method of data communication for multiple stations using shared communication media within a network. A data communication message structure uses a preamble that includes both source and destination data. The message structure allows use of collision resolve logic to prioritize stations within the network such that the winner is the one with the highest priority. The destination preamble data allows each station to sample and store destination data to a buffer for decoding in the background where the station does not have to support the network data rate.

Abstract: A modem relay provides a local interface to the a modem on both ends of a call, demodulates the full duplex data stream, packetizes the bits for transport over an IP network, and remodulates the data stream at the remote end. The modem relay negotiates a best supported rate and modulation. If no common rate and modulation is supported by the modems at each end of the communication, the modem relay components will establish independent connections to the modems at each end and transmit information across the packet network. The modem data stream can also be transported in a redundant fashion, which allows for seamless error recovery in the event of single or double packet loss events. Since the data stream can be completely recovered after packet loss, the remote modem is able to recreate the local modem's transmission exactly.