Abstract: An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.

Abstract: The self-clustering of service processors within a system is disclosed. The system can also include an operating system or other software code, a management console, or both. The operating system communicates with the cluster of service processors, where the service processors are self-clustered or otherwise, such as through a memory shared by at least all the service processors. The operating system therefore need not be aware which of the service processors performs a given function. The console communicates with the cluster of service processors, where the service processors are self-clustered or otherwise, through any service processor of the cluster. The console therefore also need not be aware that the service processors have been clustered to perform functionality for the console.

Abstract: A high-level language, architecture-independent probe program compiler is disclosed. A base program is executable by one or processors, and has one or more breakpoints. A probe program is associated with each breakpoint and is also indirectly executable by the one or more processors. The probe program is independent of the architecture of the processors, and is generated from source code written in a high-level language. The probe program associated with each breakpoint is executed when the breakpoint is reached during execution of the base program. The compiler may employ an abstract syntax tree to switch between an address space of the probe program and an address space of the base program, by traversing the tree. Some of the nodes of the tree may more simply represent address space-specific objects of the base program. The probe program may be able to pass messages by manipulating the state of the base program.

Abstract: Non-inline transaction error correction is disclosed. Where a transaction being processed in a pipeline is determined to include a correctable error, it is output, or drained, from the pipeline into an error queue. The pipeline is switched from a normal mode of operation to a correction mode of operation. In the correction mode, a correction command is inserted into and processed within the pipeline to correct the error within the transaction. The pipeline is switched from the correction mode of operation to a restart mode of operation. In the restart mode, the transaction is reprocessed within the pipeline. The pipeline is then switched from the restart mode of operation back to the normal mode of operation.

Abstract: Mobile node registration with the home network of the mobile node is delayed when the mobile node moves to a foreign network. The mobile node has a home network in which the mobile node has a home address. In response to the mobile node moving to a foreign network (such as by being turned on in the foreign network), the mobile node receives a care-of address. Where the mobile node has no ongoing communication sessions, the mobile node waits to register its care-of address with its home agent in the home network until the mobile node initiates a communication session within the foreign network, which may not ever occur. The mobile node by registering the care-of address with the home agent informs the home agent where to forward data sent to the mobile node's home address.

Abstract: Read-copy-update (RCU) is performed within real-time and other types of systems, such that memory barrier usage within RCU is reduced. A computerized system includes processors, memory, updaters, and readers. The updaters update contents of a section of the memory by using first and second sets of per-processor counters, first and second sets of per-processor need-memory-barrier bits, and a global flip-counter bit. The global flip-counter bit specifies which of the first or second set of the per-processor counters and the per-processor need-memory-barrier bits is a current set, and which is a last set. The readers read the contents of the section of the memory by using the first and second sets of per-processor counters, the first and second sets of per-processor need-memory-barrier bits, and the global flip-counter bit, in a way that significantly reduces the need for memory barriers during such read operations.

Abstract: Atomic renaming and moving of data files, while permitting lock-free look-ups to the data files, is disclosed. A temporary record may be created within a hash chain encompassing a record for a data file and corresponding to a location of the data file within a computer file system. The temporary record is linked within the hash chain so that the temporary record points to the same records to which the record for the data file points. The record for the data file is renamed with a new name, and/or moved to a new location within the computer file system, and the temporary record is removed from the hash chain. Before the temporary record is removed, look-ups of the data file resolve to the temporary record, the temporary record causing the look-ups to wait until the record for the data file has been renamed and/or moved and the temporary record removed.

Abstract: Determining an error-correcting code (ECC) for a cache entry based at least on the data stored in the cache entry and the memory address at which the data is permanently stored is disclosed. A cache entry for a desired memory address is retrieved. The cache entry includes data and a stored ECC based on the data and a memory address. An ECC is determined based at least on the data of the cache entry and the desired memory address. If the ECC at least based on the cache entry data and the desired memory address equals the stored ECC, then the cache entry caches the desired memory address without error.

Abstract: An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.

Abstract: Redefined hardware structured transactions and the associated responses in a data processing device are made user programmable. Three registers, a identifier register, a mask register and a response register, are used to redirect transactions or other operations within an application specific integrated circuit after post-silicon testing has been completed and there is no opportunity to redirect the hardware logic contained therein. When enabled, the registers allow for the insertion of blank table entries that can be programmed at a later time to handle unexpected output responses which occur due to unforeseen problems in the preprogrammed operation of the device. Transaction redirection can be accomplished on selected fields of identified transactions. The method is applicable to any hardware device in which it is desired to redirect actions originally defined in look-up tables when such tables are not capable of adjustment or alteration without redesign or re-manufacture.

Abstract: Secure inter-node communication is disclosed. The hardware of the first node sends a key, identification of the first node, and identification of a second node to hardware of the second node. The hardware of the second node receives the key and the identifications. The hardware of the second node verifies the identifications of the first and the second nodes, and stores the key. The key stored in the hardware of the first and the second nodes allows for a secure transmission channel from the software of the first node to software of the second node.

Abstract: Memory allocation to multiple computing units is disclosed. A static offset for each computing unit is determined, and a portion of memory is allocated for each computing unit, and remapped into a contiguous logical region that is addressable by a pointer plus the static offset. The portion of the memory is dynamically passed out to each computing unit as the computing units need memory. Upon the initial contiguous memory being completely passed out to the computing units, a number of physically non-contiguous sections of memory are mapped into another logically contiguous section of memory. A portion of this logically contiguous section of memory is allocated for each computing unit, and is addressable by a pointer plus the static offset that was previously determined. The portion of the logically contiguous section of memory can be dynamically passed out to each computing unit as the computing units need memory.

Abstract: A multiple-stage pipeline for transaction conversion is disclosed. A method is disclosed that converts a transaction into a set of concurrently performable actions. In a first pipeline stage, the transaction is decoded into an internal protocol evaluation (PE) command, such as by utilizing a look-up table (LUT). In a second pipeline stage, an entry within a PE random access memory (RAM) is selected, based on the internal PE command. This may be accomplished by converting the internal PE command into a PE RAM base address and an associated qualifier thereof. In a third pipeline stage, the entry within the PE RAM is converted to the set of concurrently performable actions, such as based on the PE RAM base address and its associate qualifier.

Abstract: The management of transactions received by a coherency controller is disclosed. A method of an embodiment of the invention is performed by a coherency controller of a plurality of coherency controllers of a node that has a plurality of sub-nodes. The coherency controller receives a transaction from one of the sub-nodes of the node. The transaction may relate to another sub-node of the node. However, the coherency controller nevertheless processes the transaction without having to send the transaction to another coherency controller of the node, even though the sub-node from which the transaction was received is different than the sub-node to which the transaction relates. The plurality of coherency controllers is thus shared by all of the plurality of sub-nodes of the node.

Abstract: A method is provided for allocating system resources across multiple nodes of a system communicating through a hardware device. The method provides for allocation of transaction units or identifiers in an allocating component for use in a multiple target component which may be in a distinct target node within the multiple node system. Based on the operations or requests that a target node receives from multiple external request source nodes, each requiring the use of target transaction unit objects such as transaction identification bits, the method provides inclusion of such information in the initial request to a target node which allows any data transmission between the source node and the target node, or the target node and the source node to be accomplished without any further intervention by the allocating component. Such component may be a local memory control agent or device.

Abstract: The access of private memory of nodes in a multi-node system is disclosed. A base node of such a coalesced system instructs at least one other node of the system to start a process related to private memory. Each of the other nodes starts the process, where the process access private memory of the node. When the process is finished on a node, the node reports back results of the process to the base node.

Abstract: Allocating potentially needed resources for a transaction before having completely received the transaction is disclosed. An initial part of a transaction is received in first clock cycle. The resources potentially needed by the transaction are determined based on the initial part thereof that has been received, and allocated. The transaction then proceeds. The final part of the transaction is received in a final clock cycle. The resources actually needed by the transaction from the resources previously allocated are determined based on the remaining part thereof that has been received. Any unneeded remaining resources are then deallocated.

Abstract: Information regarding memory access by other nodes within a coherency controller of a node is locally stored. The coherency controller receives a transaction relating a line of local memory of the node. In response to locally determining that the line of the local memory is not being cached by another node and/or has not been modified by another node, the coherency controller processes the transaction without accessing tag directory information regarding the line. A table within the controller may store entries corresponding to local memory sections. Each entry includes a count value tracking a number of lines of the section being cached by other nodes, and a count value tracking a number of lines of the section that have been modified by other nodes. The table may also include flags corresponding to the sections, each flag indicating the validity of the section's contents.

Abstract: Managing access control within system topologies by using canonical access control representations is disclosed. A set of accessor-accessible pairs is determined. Each accessor has a predetermined level of access to its paired accessible within a system topology. For each unique accessible within the set of pairs, the accessors that are paired with it are sorted and merged as a first proto-zone. For each unique subset of accessor(s) within the set of first proto-zones, the accessibles that are associated with it are sorted and merged as a second proto-zone. The second proto-zones are sorted to yield a canonical set of zones. Each zone has accessor(s) and accessible(s). The canonical set of zones is used to manage the access control of the accessors and the accessibles within the topology.

Abstract: A masterless approach binds multiprocessor building blocks to partitions of a computer system using identifiers and indicators. A number of building blocks communicate among each other to determine a partition to which each building block is to be partitioned. For each unique partition to which one or more of the building blocks is to be partitioned, the building blocks communicate among each other to determine building block uniqueness, and then each of the building blocks joins the partition. The building blocks share with one another their logical port identifiers, which uniquely identify the building block within a partition. A commit indicator of each building block indicates that the building block has committed itself to the partition and that its identifiers cannot be changed.