Abstract: An integrated circuit includes first and second power supply voltage terminals, a voltage controlled oscillator (VCO), and a deep N-well field effect transistor (FET). The VCO has a first node coupled to the first power supply terminal, a second node, and first and second oscillator output terminals, at least one of which is coupled to a common pin. The deep N-well field-effect transistor (FET) has a first terminal coupled to the second node of the voltage controlled oscillator, a second terminal coupled to the second power supply terminal, and a control electrode to receive a power on signal, a deep N-well is coupled to the first power supply terminal and a P-channel is coupled to the second power supply terminal to form a high impedance electrostatic discharge path between the common pin and the first and the second power supply terminals through the deep N-well.

Abstract: A mixer (114) includes a phase clock generator (404), a latch (420), and a multiplier (118). The phase clock generator (404) provides a plurality of phase clock signals. The latch (420) is coupled to the phase clock generator (404) via a first plurality of conductors (410) and provides a plurality of resynchronized phase clock signals. The multiplier (118) is coupled to the latch (420) via a second plurality of conductors (430) and mixes an input signal using the plurality of resynchronized phase clock signals to provide a mixed output signal. The second plurality of conductors (430) is characterized as having a lower end-to-end impedance than an end-to-end impedance of the first plurality of conductors (410).