Abstract: A direct connect mesh routing structure is provided for interconnecting configurable logic blocks within a programmable logic device. The structure includes multi-bit interconnect busses and a highly regular structure distributed throughout a configurable array enabling high direct interconnect utilization to adjacent and non-adjacent logic blocks, high speed circuit implementation, and improved timing characteristics. The direct connections of the invention are the preferred interconnect path between logic blocks because they substantially reduce the average interconnect delay, thereby allowing the programmable logic device to operate at a higher speed.