Abstract: A method and software apparatus are provided for implementing a dynamically modifiable test flow for integrated circuit devices that adapts to the characteristics of each processed device lot. According to the method of the invention, a modified set of tests sufficient to ensure proper device function for a particular lot is performed, reducing test costs and increasing test capacity. The method and system of the invention periodically samples a predetermined sample number of devices using a full set of tests including a set of skippable tests. Depending upon the performance characteristics of the sample device group on the skippable tests, a number of skippable tests are skipped during a modified test flow. After a next set of devices is tested using the modified test flow, the full set of tests is again performed on another sample group, and the size and makeup of the modified test flow is adjusted according to the new results.

Abstract: A method and system are provided for increasing the accuracy of AC parametric testing. The invention provides a method of precisely estimating signal propagation delay time in an integrated circuit testing apparatus, wherein a plurality of signal propagation delay time measurements are taken and additional delay times are estimated by linearly interpolating the measured delays. A desired test point (desired output voltage at a given time) is established. Using a sample device, a slope is established on a time vs. voltage plot for a line through the desired test point. Where a desired test point falls between strobe times on a tester, linear extrapolation is used to calculate what voltages must be tested for at the two bracketing strobe times in order to guarantee the desired performance at the desired test point. One or more devices are then tested for the calculated voltages at the corresponding bracketing strobe times.

Abstract: A system and method are provided for selectively inferring latch elements in a circuit design from an event-driven hardware description language (HDL) file to an event-independent format. The method includes modeling the file as a plurality of data flow equations, analyzing the plurality of equations for uninitialized variables, and placing a latch at any utilized, uninitialized variable. Control signal information for an inferred latch is also derived during the data flow analysis.

Abstract: A method is provided for scan testing that eliminates the need for balancing internal scan clock delays. According to the method of the invention, multiple scan clocks are provided, each being provided to a different set of flip-flops. The skew between the active edges of the scan clocks is deliberately increased to the point where each set of flip-flops has plenty of time to settle before the next set of flip-flops receives a clock pulse. Because scan testing is typically performed at clock speeds of only about 1 Megahertz, there is time for each of the scan clocks to pulse separately from all the others, without increasing the test time. The increased delay between scan clock pulses eliminates the need for balancing internal delays on the scan clock paths, thereby greatly reducing the number of placement and routing iterations required to achieve a functional design.

Abstract: A method for operating a microprocessor controlled, reel type slot machine in which payoff is determined before a final game outcome is displayed to a player. A pre-defined count of random numbers is generated and presented to a digital filter having tap outputs which correspond to paytable payline equations. The minimum number of payline equations is equal to the number of distinct paylines in the paytable plus one. Any changes in game outcome are taken into account by modifying variables in computer memory and as such do not require a change in tables stored in computer memory. Several features for attracting players to the apparatus and increasing the enjoyment of playing a game are included.

Abstract: A method is disclosed for automatically updating the status of customers' orders and shipments via electronic mail without using a human attendant to create and send the electronic mail messages. Preferably implemented in software, the updating method allows a large set of customers to be periodically updated over a computer or communications network via electronic mail. The method utilizes a database for maintaining order and shipping status and other relevant information.

Abstract: A multi-state input drive structure is provided to forward externally generated high and low input signals, as well as to receive at least a third, internally generated, comparatively weak signal, preferably an oscillating signal, which triggers a third internally forwarded signal when neither of the high and low input signals is received. The inventive circuit drives three internally forwarded output signals from a single external signal source. Since this circuit may be duplicated for every pin on a device for which two cycle delays do not affect performance, availability of a third input state on N inputs allows 3.sup.N input codes as opposed to 2.sup.N for the conventional "high" and "low" levels normally available.

Abstract: An exercise apparatus for stimulating muscle coordination and joint stability through multiaxial movement patters involving rotation force is provided. A plurality of methods of use of the apparatus are presented as well to maximize the therapeutic and preventative benefit of the apparatus. A variety of embodiments, including a portable version, are described.

Abstract: A method is described for testing the programming function of integrated circuit device cells including floating gate elements. To accelerate the testing process, at most two programming pulses are needed, the two pulses being applied with the device at minimum and maximum power supply voltage levels specified for the device. First, the cell state after an initial programming pulse with the device at a minimum power supply voltage level, tested against a minimum reference voltage level, indicates whether the cell is programming properly. If not, testing ceases immediately and the device is rejected after the first pulse. Devices passing the first reading after the first pulse are subjected to a second reading at the target (higher) reference voltage. Devices passing after the second reading are designated as passing and are subjected to the next test in the test flow.

Abstract: An improved arithmetic logic unit (ALU) of an erasable-programmable logic device (EPLD) with a flexible, programmable carry function allows a broad range of functions to be implemented. The inventive circuit utilizes a separately configurable carry chain with multiple logic and arithmetic function capabilities.

Abstract: A real time video processing system adds a programmable logic device between a conventional frame buffer and a conventional digital to analog converter to provide real time and off-screen processing power to enhance video output capabilities. The system may include a history FIFO connected to deliver the preceding line to the programmable logic device, allowing operations on a pixel in the current line, modified as needed by the status of one or more nearby pixels. The system may also include inputs for multiple video sources and may include input FIFOs for more random access to portions of the input stream. An alternative form of the system includes a crossbar switch and multiple memory devices, to allow switching among several possible frame buffer devices. One or more processing units can be added to manipulate a memory which is not the active frame buffer. The programmable logic device can be loaded with a configuration file stored in an associated memory or loaded from a host computer.

Abstract: A system and method for conducting a multi-person, interactive auction, in a variety of formats, without using a human auctioneer to conduct the auction. The system is preferably implemented in software. The system allows a group of bidders to interactively place bids over a computer or communications network. Those bids are recorded by the system and the bidders are updated with the current auction status information. When appropriate, the system closes the auction from further bidding and notifies the winning bidders and losers as to the auction outcome.

Abstract: A method and apparatus for creating and utilizing a database of defective antifuses on a programmable logic device and comparing the list to a catalog of required connections in a design, wherein the process of comparing the two lists will determine whether the device, although flawed, is nonetheless compatible with the design to be implemented, thereby increasing device yield.

Abstract: A method and apparatus for loading memory within a reconfigurable programmable logic device including configuring the device as a RAM loader circuit, loading the RAM with data and then reconfiguring the device with a circuit utilizing the loaded RAM. The inventive method and apparatus allow use of the RAM as high density functional centers of the desired design immediately upon initialization of the circuit, without wasting valuable time or FPGA resources on a static, non-flexible RAM loader structure.

Abstract: An alternating current (AC) spike absorption circuit employs a pair of back-to back parallel high-speed ultra-soft recovery diodes with unique RFI prevention characteristics. Further high frequency noise suppression is achieved by using a high voltage parallel-connected capacitor and a plurality of series-connected parallel ceramic-type resistors which are formed by resistors having coil windings providing an equivalent circuit of parallel resistance and inductance. The inductance provides ultra high frequency rejection and the resistance provides damping of any ringing oscillation. A surrounding ceramic material casing of the ceramic-type resistors resists the transmission of radio frequency energy.

Abstract: In an FPGA having a hierarchical routing structure, additional routing lines are provided which have different destinations for different cells within a block. A pattern is chosen which allows signal lines to turn corners conveniently. In one embodiment having cells arranged into 4.times.4 blocks, cells on the diagonal of a block generate signals which are provided to switches which form one boundary of the block.