Patents Represented by Attorney Adeli Law Group
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Patent number: 7353274Abstract: Some embodiments provide a method of determining whether a lottery player or the player's computer is within a particular location. The player's computer is connected to a computer network. The method transmits, through the computer network, a pass code and a telephone number to the lottery player's computer. The method requests the lottery player or the player's computer to call the number and provide the pass code within a pre-determined amount of time. The method determines whether the pass code is provided within a predetermined amount of time after the transmission of the pass code from a telephone specified to be within the particular location. The method verifies whether the lottery player or player's computer is within the particular location, based on the determination.Type: GrantFiled: May 9, 2000Date of Patent: April 1, 2008Assignee: Medisys/RJB Consulting, Inc.Inventors: Adam G. Rouhi, Ramin Ron Rouhi
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Patent number: 7317331Abstract: Some embodiments provide a reconfigurable IC that includes several sections. Each section includes several configurable circuits, each of which configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that the particular configurable circuit has to perform from the circuit's set of operations, where the configurable circuits of at least two different sections change configuration data sets at two different reconfiguration rates.Type: GrantFiled: March 15, 2005Date of Patent: January 8, 2008Assignee: Tabula, Inc.Inventors: Steven Teig, Herman Schmit, Jason Redgrave
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Patent number: 7312630Abstract: Some embodiments provide a configurable integrated circuit (“IC”) with a configurable node array. A configurable node array may include configurable nodes arranged in rows and columns. It may also include direct offset connections, with each direct offset connection connecting two nodes that are neither in the same column nor the same row. In some embodiments, at least some direct offset connections connect pairs of nodes that are separated by more than one row and at least one column, or by more than one column and at least one row. Some embodiments establish a direct connection by a set of wire segments that traverse through a set of the IC's wiring layers, and a set of vias when multiple wiring layers are involved. Some of the direct connections may have intervening circuits (e.g. buffer circuits). In some embodiments, the nodes in the array are all similar to each other.Type: GrantFiled: June 30, 2004Date of Patent: December 25, 2007Assignee: Tabula, Inc.Inventors: Andre Rohe, Steven Teig
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Patent number: 7301242Abstract: Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC's that are arranged within the single IC housing. At least one of the IC's is a configurable IC. In some embodiments, the configurable IC is a reconfigurable IC that can reconfigure more than once during run time. In some of these embodiments, the reconfigurable IC can be reconfigured at a first clock rate that is faster (i.e., larger) than the clock rates of one or more of the other IC's in the PSiP. The first clock rate is faster than the clock rate of all of the other IC's in the PSiP in some embodiments.Type: GrantFiled: March 15, 2005Date of Patent: November 27, 2007Assignee: Tabula, Inc.Inventor: Steven Teig
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Patent number: 7301368Abstract: Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits. The routing circuits of the tiles configurably route signals between configurable logic circuits. Each memory tiles includes a set of routing circuits and a memory array for storing data on which the logic circuit perform computation. In this IC, at least a first memory tile has the same set of configurable routing circuits as at least a second computational tile.Type: GrantFiled: March 15, 2005Date of Patent: November 27, 2007Assignee: Tabula, Inc.Inventors: Herman Schmit, Jason Redgrave
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Patent number: 7298169Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit can interchangeably perform as either a logic circuit or an interconnect circuit in the configurable IC.Type: GrantFiled: March 15, 2005Date of Patent: November 20, 2007Assignee: Tabula, IncInventors: Brad Hutchings, Herman Schmit, Jason Redgrave
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Patent number: 7272803Abstract: A method for defining and producing a power grid structure (having stripe, rail, and via components) of an IC. The method reduces the number of vias in the power grid structure and the diagonal wiring blockage caused by the vias while still meeting design specifications. Other embodiments provide a method for locating vias in the power grid structure in such a way as to be especially beneficial to 45° or 135° diagonal wiring paths. The method includes processes of a power grid planner, power grid router, power grid verifier, and global signal router that are used iteratively to define and produce a power grid structure. Other embodiments of the invention provide for arrangements of vias in via arrays where diagonal wiring paths are facilitated near the edges of the via arrays. A bounding box enclosing these via arrays have an aspect ratio that is approximately equal to 1.Type: GrantFiled: June 1, 2003Date of Patent: September 18, 2007Assignee: Cadence Design Systems, Inc.Inventor: Hengfu Hsu
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Patent number: 7262633Abstract: Some embodiments provide a via programmable gate array (“VPGA”) with several configurable circuits arranged in a configurable circuit arrangement. At least some of the configurable circuits are via programmable (“VP”) configured circuits. In some embodiments, the configurable circuit arrangement is a configurable circuit arrangement that includes numerous (e.g., 50, 100, etc.) configurable circuits that are arranged in several rows and columns. This circuit arrangement also includes several bit lines, where at least one the bit line provides a configuration value to at least one configurable circuit. In some embodiments, at least some bit lines transverse along more than one column or row in the circuit arrangement.Type: GrantFiled: November 11, 2005Date of Patent: August 28, 2007Assignee: Tabula, Inc.Inventors: Herman Schmit, Steven Teig
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Patent number: 7260504Abstract: Some embodiments of the invention provide a system for monitoring liquid consumption at one or more establishments. At each establishment, the system includes one or more spouts and a local computer. Each spout is mounted on a liquid container. Also, each spout generates data regarding the amount of liquid poured from the spout's container. The local computer at each establishment collects data generated by the spouts at the establishment. In some embodiments, a wireless network links the local computer and the spouts at each establishment. The system also includes an external computer that gathers the data collected by the local computers of the establishments monitored by the system. In some embodiments, the external computer is located outside of all the establishments, while in other embodiments this computer is located within one of the establishments. Some embodiments of the invention provide a free-pour spout.Type: GrantFiled: January 9, 2006Date of Patent: August 21, 2007Assignee: Capton, Inc.Inventor: Masoud Mike Mogadam
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Patent number: 7254798Abstract: A method for modifying an upper layout for an upper layer of an IC using information of a lower layout for a lower layer of the IC, the method including 1) receiving the upper layout containing features and modifications to features, 2) producing a density map of the lower layout having geometry coverages of sub-regions of the lower layout, 4) selecting a feature in the upper layout, 5) retrieving, from the density map, the geometry coverage of a sub-region below the feature, 6) determining a vertical deviation of the feature using the geometry coverage, 7) determining an alteration to the modification using the vertical deviation, 8) applying the alteration to the modification, and 9) repeating for all features. In some embodiments, the upper layout is designed using a library of pretabulated models, each model containing a modification to a feature calculated to produce a satisfactory feature on a wafer.Type: GrantFiled: May 1, 2004Date of Patent: August 7, 2007Assignee: Cadence Design Systems, IncInventors: Louis K. Scheffer, Steven Teig
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Patent number: 7249168Abstract: A method and apparatus for remotely and automatically mounting volumes over a network. The invention uses an interface, such as a web browser, to authenticate a client on a server. The server supplies volume mounting parameters specific to the authenticated client via a plug-in installed on the client. The plug-in then interacts, in one embodiment of the invention, with file system software on the client and automatically mounts the volume(s) in accordance with the supplied parameters.Type: GrantFiled: December 28, 2000Date of Patent: July 24, 2007Assignee: Apple Inc.Inventor: Scott Ryder
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Patent number: 7245916Abstract: An unlicensed wireless service is adapted to generate the interface protocols of a licensed wireless service to provide transparent transition of communication sessions between a licensed wireless service and an unlicensed wireless service. In one embodiment, a mobile station includes level 1, level 2, and level 3 protocols for licensed wireless service and an unlicensed wireless service. An indoor base station and indoor network controller provide protocol conversion for the unlicensed wireless service into a standard base station controller interface of the licensed wireless service.Type: GrantFiled: September 12, 2005Date of Patent: July 17, 2007Assignee: Kineto Wireless, Inc.Inventors: Michael D. Gallagher, Jahangir Mohammed, Joseph G. Baranowski, Jianxiong Shi, Milan Markovic, Thomas G. Elam, Kenneth M. Kolderup, Madhu C. Shekhar, Mark Powell
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Patent number: 7246338Abstract: Some embodiments of the invention provide a method for costing an expansion to a two-dimensional state in a path search that searches for a path between two sets of states in a space. The method identifies a cost function that is defined over the two-dimensional state. The method computes a second cost function that is defined over the two-dimensional state. It also computes a third cost function that is defined over the two-dimensional state. It then adds the second and third cost functions to obtain the first cost function.Type: GrantFiled: December 31, 2002Date of Patent: July 17, 2007Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Andrew Caldwell
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Patent number: 7242411Abstract: A method for processing an image of a given file type is disclosed. The method involves converting the image into data formatted for a new pixel type, the new pixel type is closely correlated with and has all the components of pixels for the given file type. In addition, the method includes processing the data formatted in the new pixel type using standard image processing routines, these standard routines being designed for data having different components of pixels than the new pixel type and the given file type.Type: GrantFiled: March 2, 2004Date of Patent: July 10, 2007Assignee: Apple Inc.Inventors: Eric Graves, Randy Ubillos
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Patent number: 7243328Abstract: Some embodiments of the invention provide novel methods for representing items in a design layout. For instance, they use a method that identifies several half-planes, that when intersected, define the shape of the item. Some embodiments use a method that (1) identifies a first set of location data for the item with respect to a first coordinate system, (2) identifies a second set of location data for the item with respect to a second coordinate system, and (3) specifies the item in terms of the first and second set of location data. In some embodiments, both the first and second coordinate systems have first and second coordinate axes. Some embodiments use a method that receives a first set of data that defines the item with respect to a first coordinate system of the design layout.Type: GrantFiled: May 21, 2003Date of Patent: July 10, 2007Assignee: Cadence Design Systems, Inc.Inventors: Etienne Jacques, Tom Kronmiller
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Patent number: 7242216Abstract: Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. These tiles are arranged in a particular tile arrangement. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits. The routing circuits of the tiles configurably route signals between configurable logic circuits. The configurable IC also has several memory arrays for storing data on which the logic circuit perform computation. The memory arrays are embedded in the tile arrangement between two sets of memory tiles, where each set of memory tiles includes a set of routing circuits. In this IC, at least a first memory tile has the same set of configurable routing circuits as at least a second computational tile.Type: GrantFiled: March 15, 2005Date of Patent: July 10, 2007Inventors: Herman Schmit, Jason Redgrave
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Patent number: 7239721Abstract: Some embodiments of the invention provide a method of performing motion estimation for an array of image values obtained from a current image. The method starts with an initial estimate of the motion of the current image. The method then determines whether the initial estimate of the motion of the current image array between the current image and a reference image is acceptable. If not, the method specifies a first value for a parameter for performing the motion estimation. Otherwise, the method specifies a second value for the parameter. The method then performs a motion estimation operation based on the specified value of the parameter. One example of a specified parameter is the size of the window that the motion estimation operation uses. Another example is the starting level for a hierarchical motion estimation operation that it performs. A hierarchical motion estimation operation searches the reference frame at several different levels of granularity.Type: GrantFiled: April 30, 2003Date of Patent: July 3, 2007Assignee: Apple Inc.Inventors: Roger Kumar, Thomas Pun, Xiaochun Nie, Hsi-Jung Wu
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Patent number: 7236009Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.Type: GrantFiled: March 15, 2005Date of Patent: June 26, 2007Inventors: Andre Rohe, Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell