Abstract: A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the internal ground.

Abstract: The application discloses driver circuits including a current source, a current sink, and a current steering circuit configured to provide current to a load. The current sink is configured to be controlled according to a regulated voltage. Signal generator circuits are also disclosed.

Abstract: In one application, a method according to an embodiment of the invention is used to enable a display of proportionally spaced characters using a fixed-font display controller.

Abstract: A dynamic buffer is used to display an object from a document. The cut object is visible to the user as the floating cursor is positioned to a desired insertion point. The cut object can be any combination of text, graphics or data. The display can move in conjunction with the floating cursor or be parked at a predetermined or user-selected position. The cut object can be abbreviated to fit the display, or the display can be sized or scrolled. Once an object has been cut and thus stored in the dynamic buffer, it can be edited, or pasted to a new location or merely deleted.

Abstract: An audio data compression method improves over existing standards because of its encoding strategy for silence. The method analyzes the audio input to an encoder. If the audio is for an analyzed time frame is silence, a single byte output is generated by the encoder. If the next frame is silence, no output is generated. When a receiver receives the compressed data, and detects a one-byte silence signal, it can capture that signal and repeat it to a decoder. When the compressed signal reaches the decoder, it is decompressed into an analog signal.

Abstract: The present invention relates to multiprocessors which has several microprocessors on a single chip. Efficiency is improved by stripping certain functions that are used less freely from the microprocessor and sharing these functions between several symmetric microprocessors. This method allows each CPU to occupy a smaller area while preserving complete symmetry of capability for software simplification. For example, the shared execution units can include the floating point unit and multimedia execution units.

Abstract: A shift register is used to latch the bus-driver-enable signal for each potential bus driver during each system clock cycle. The shift register clock will freeze upon receipt of a "check stop" signal. Once frozen, the shift register can be scanned for fault isolation analysis.

Abstract: A computer system including a memory controller programmed with associated burst order translation logic and coupled to one or more microprocessors and including a memory circuit which supports either sequential or interleaved transmission of burst data communication between an I/O devices and one or more of the microprocessors. Data transmitted to or from an I/O device, processor or memory is temporarily stored in a buffer within the memory controller. The buffers contain multiple addresses with each address capable of containing a quadword of data. The quadwords of data are transferred to the addresses corresponding to which quadword is the requested quadword from the processor. The quadwords are transmitted, requested quadword first then the next quadword, continuing until all quadwords are transmitted. The corresponding addresses are determined through incrementing or decrementing a pointer to the corresponding addresses, dependent upon the burst ordering translation required.