Abstract: An asymmetry detection apparatus includes: a clock signal generator for generating a clock signal based on a reproduced signal; an A/D converter for sampling the reproduced signal in synchronization with the clock signal; a determiner for determining whether a level of each of a plurality of sampled data obtained by the sampling operation is equal to or greater than a predetermined level; and a detector for detecting asymmetry in the reproduced signal by using predetermined ones of the sampled data based on an output from the determiner.

Abstract: A video compression method is provided and implemented in a pixel processing controller of a digital solid-state imaging device for maximizing throughput of digitized video data on a link between the digital solid-state imaging device and a host computer. The method performs separate luminance (Y) domain compression of the video data on a line-by-line basis, without storing video data lines or video data frames, and separate chrominance (Cr/Cb) domain averaging of the video data on a region-by-region basis without storing video data in video frames. The Y and Cr/Cb domain compression steps are implemented in the digital solid-state imaging device hardware for real time link transmission of the compressed video data to the host computer.