Abstract: An electronic half adder circuit wherein an entire word of either 16 or 32 bits is divided into stages, carry is rippled within each stage and look-ahead carry is computed between the stages, having a dual gate look-ahead carry circuit for propagating a look-ahead carry bit between said stages. This is also a processor system. The system includes: memory for storing program instructions; a processor coupled to the memory for receiving predetermined ones of the program instructions; the processor comprises: an arithmetic unit; control circuitry for controlling the arithmetic unit in response to selected ones of the predetermined program instructions; a counter coupled to the control circuitry comprising half adder circuitry wherein a dual gate look-ahead carry circuit for propagates a look-ahead carry bit between the stages.