Abstract: In accordance with this invention, a remote control for an interactive media can include a printed publication and/or a storage media and/or a data button. One embodiment of a remote control includes a printed publication (such as a book, magazine or a catalog) and one or more buttons physically attached to the printed publication to allow users to remotely control use of associated electronic content by a host device. Another embodiment of a remote control has a housing capable of removably holding a storage media encoded with electronic content associated with a button of the remote control. Yet another embodiment of a remote control has at least one data button which permits the user to select the data to be displayed by the host device. An autostart driver in the host device detects insertion of a storage media into a peripheral and automatically starts an application. The application interprets button codes transmitted by the remote control and displays the results or initiates other events.

Abstract: Like a conventional one-way pager system, a two-way pager system is provided in which a message is received by paging from a base station and a message responding to the received message is returned to the base station. In this system, direct communication and peer-to-peer communication between terminals are performed. All the terminals included in the service area of the base station are always synchronized with sync signals paged from the base station. No special infrastructure is therefore required for synchronizing the terminals with the sync signals to perform the peer-to-peer communication. Furthermore, since each of the terminals receives a paging signal during the peer-to-peer communication, it can respond to a paging call.

Abstract: A structure for improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, a substrate has an upper surface and a first dopant region formed therein. The first dopant region has a lower boundary located below an upper surface of the substrate and a side boundary extending from the upper surface of the substrate to the lower boundary of the first dopant region. A heavily doped region having a first portion and a second portion located along the lower boundary and the side boundary of the first dopant region, respectively, has a substantially uniform dopant concentration greater than a dopant concentration of the first dopant region. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.

Abstract: An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.

Abstract: A screw shaft feed mechanism includes a screw shaft (25) rotatably supported by a frame (19) and extending in a shaft feed direction of a work table (shaft fed base) (1); a nut member (39) rotatably supported by the work table (1) and engaged with the screw shaft (25); a screw shaft drive motor (29) for rotating the screw shaft (25); and a nut drive motor (57) for rotating the nut member (39), wherein both screw shaft driving means and nut driving means are provided with a motor having a device detecting a rotational angle of a motor shaft, respectively.

Abstract: A structure especially useful in a configurable logic array includes a plurality of conductive interconnect lines located along the perimeter of a logic array chip. Lines running from exterior pins or pads can be used by a programmable interconnect circuit to control signals applied to these interconnect lines. In particular, both the signal and the complement of the signal can be used by the programmable interconnect to control application of a supply voltage to an interconnect line. A second supply voltage is applied through a resistor to the interconnect line with the result that the interconnect line will carry a logical signal representing a logical function, for example AND, of a selected set of input signals or their complements. Lines running from points interior to the configurable logic array chip may also contribute to the signal generated on an interconnect line. In one embodiment, bidirectional programmable interconnect circuits allow the input pins to function as either input or output pins.

Abstract: An optical rotary encoder eliminates the necessity of relatively positioning a code plate and a click mechanism therefor so that it can be assembled with ease. The code plate is mounted for rotation relative to a stationary plate member, and the click mechanism including a ball and a spring plate is interposed between the code plate and the plate member so that all the members can be incorporated as a single device.

Abstract: A multifunction human digit control includes a rotating cylinder journalled in a movable bar slidable in a groove in a deflectable support track. Rotation of the cylinder by a thumb or finger generates a first motion signal and movement of either or both of the bar and the cylinder by tactile movement, generates a second motion signal, representing, for example, X-axis and Y-axis positions, respectively, of a cursor on a computer screen. Various types of motion detectors or encoders are disclosed to detect the various movements of the bar and cylinder. The mechanism also permits actuation of a switch or other motion detector in a Z-axis by deflection of any one of the bar, the cylinder or portions of the support track with respect to a support structure. In a preferred embodiment, the overall control has its digit-operated tactile surfaces exposed in an aperture contained in a device casing, such as an opening in a computer keyboard or in an instrument housing or control panel.

Abstract: An ECL Programmable Logic Array (PLA) having ECL voltage level compatible input and output leads, thereby providing a high-speed PLA. A unique programming means is provided which allows the ECL PLA to be programmed using TTL-compatible programming voltage levels, such as are provided by common and inexpensive prior art TTL PLA programmers. In another embodiment higher speed is achieved by the design of each sense amplifier using emitter function logic such that the sense transistor and load functions a cascode amplifier. In another embodiment a lower power PLA device is achieved by utilizing a switched current source pull down means for pulling down the rows of the PLA array. In another embodiment low power and user convenience is achieved by allowing each pair of output terminals to share a predefined set of product terms.

Abstract: A method of operating a data processing system using virtual memory in which virtual memory addresses are formed by a base register value and a displacement value and are mapped to real memory addresses includes the steps of adding the base register value content and the displacement value, and simultaneously with the adding operation, performing a translation of the base register value to produce a virtual address corresponding to the base register value.

Abstract: This inventive DMOS transistor provides faster turn-on switching than prior art lateral and vertical DMOS transistors in dV/dt situations and prevents catastrophic failures from high dV/dt's. The preferred embodiment of this improved device combines a Schottky diode with a vertical DMOS transistor, within the semiconductor structure itself, to form a device equivalent to a Schottky diode in parallel with an N channel vertical DMOS transistor. The Schottky diode effectively replaces the body diode of the transistor when forward biasing voltages are applied to the DMOS transistor. Thus, the body diode is never forward biased and there is no recovery time associated with the body diode. This speeds up the turn-on of the DMOS transistor since there are no minority carriers in the P-N junction body diode to recombine. Also, the parasitic bipolar junction transistor (BJT), formed by the source, body region, and drain, cannot turn on, thus preventing second breakdown of the BJT.

Abstract: A computer is sped up by reducing significantly the time necessary for the computer to detect and respond to an overflow following an ALU operation of a type which generates an overflow. This is done by assuring the next instruction in sequence is the one to be executed and in parallel detecting the occurrence of an overflow as the result of an implementation of a selected instruction and then producing a flag in response to the overflow. The flag is detected, and selected portions of the computer are disabled to inhibit any change in state within the computer following the generation of the overflow. An interrrupt sequence is then implemented to correct the output of the instruction which generated the overflow to compensate for the overflow. The next following instruction is then implemented after completion of the interrupt routine.

Abstract: A unique timing system is provided which allows for a user to program timing events with variable periods and edges from a fixed frequency clock, and having resolution greater than that of the fixed reference frequency. Delay elements, which are inherently expensive, inaccurate, and require repeated calibration, are minimized.

Abstract: A unique automatic test system (100) is provided in which timing signals are generated in a novel manner as compared with prior art test systems. All adjustments for propagation delays of timing signals are made in a digital fashion, by adjusting the digital information which defines when an analog timing signal is to be generated. Deskewing of propagation delays is performed automatically under computer control, rather than by requiring careful adjustment of hardware deskewing elements. By adjusting for propagation skews digitally, propagation skews dependent on data values (logical 0 and logical 1) can be made. Furthermore, timing signals are provided by three timing edges, rather than by a timing pulse, thereby allowing more accurate generation of timing signals.

Abstract: A microcoded data processing system utilizes common microcode execution routines for both register-to-register operations and memory-to-register operations. The system includes a memory data register for storing an operand for use in a memory-to-register operation, a pair of address registers for containing the addresses of the registers to be involved in the execution of register-to-register instructions, and circuitry responsive to generation of an instruction indicating a memory-to-register operation for generating the address of the memory data register from one of the address registers, whereby the register-to-register operations and the memory-to-register operations can share common execution routines without any performance time penalty or any increase in required microcode.The system also provides for the simultaneous generation of the addresses of all registers to be employed in instructions involving multipart operands.

Abstract: A compact particle flux monitor is formed with an enclosure through which a laser beam is directed by a lens. An aperture in the enclosure allows free particles which are to be detected to pass through a sensing area at a limiting acceptance angle thereby providing an indication of direction of particle flow. Photodiodes mounted at the sensing area detect the particles, including relatively small particles, by means of the high intensity beam portion at the region of the focal point of the light beam. The response region along the diverging beam is relatively long so that the response as a function of particle size is above background noise level.

Abstract: The imaging system includes widely-spaced sensors on an airborne vehicle providing a base-line distance of from about five to about 65 meters between the sensors. The sensors view an object in adjacent air space at distances of from about 0.3 to 20 kilometers. The sensors may be video cameras or radar, sonar infrared or laser transponders. Two separate images of the object are viewed by the spaced sensors and signals representing each image are transmitted to a stereo display so that a pilot/observer in the aircraft has increased depth perception of the object. In effect the interpupillary distance of the human viewer is increased from the normal 5.9-7.5 cm to from about 5 to about 65 meters resulting in depth perception of objects at a distance of from about 0.3 km to 20 km or more.

Abstract: In a memory circuit including a write bit-line for writing data into a memory cell, and a read bit-line for reading data from the cell, a transistor is included, connected with the write bit-line and the read bit-line, so that when a fast flush signal is applied to the gate of that transistor, direct connection is made between the write bit-line and read bit-line, so that data is written into the cell, but can be read simultaneously from the read bit-line, reducing the fall-through delay.

Abstract: A particle detector includes a laser, a beam shaping lens, and a pair of mirrors which reflect the shaped laser beam back and forth between the mirrors a selected number of times in order to create a sheet of light or light net between the mirrors. The path of the beam is terminated by a beam stop which contains a photodiode to monitor beam intensity and thereby system alignment. Light scattered by a particle falling through the sheet of light is gathered and transmitted to a photodiode. A peak detector provides a measure of the peak intensity of light scattered by such a particle to a microprocessor, which counts the number of particles falling through the light net in a selected time interval. The microprocessor also uses the peak intensity to estimate the size of the particle.

Abstract: A configurable logic array comprises a plurality of configurable logic elements variably interconnected in response to control signals to perform a selected logic function. Each configurable logic element in the array is in itself capable of performing any one of a plurality of logic functions depending upon the control information placed in the configurable logic element. Each configurable logic element can have its function varied even after it is installed in a system by changing the control information placed in that element. Structure is provided for storing control information and providing access to the stored control information to allow each configurable logic element to be properly configured prior to the initiation of operation of the system of which the array is a part. Novel interconnection structures are provided to facilitate the configuring of each logic element.