Abstract: In some embodiments, a chip includes a memory core, error detection circuitry, and a control unit. The error detection circuitry determines the validity of error detection signals associated with speculative and non-speculative commands received by the chip and to provide validity signals indicative of the determined validity. The control unit provides the speculative commands to the memory core to be acted on before the control unit receives the associated validity signals and to provide the non-speculative commands to the memory core to be acted on only after receiving associated validity signals that indicate the associated error detection signals are valid. Other embodiments are described and claimed.

Abstract: In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.

Abstract: A memory includes a data generator to generate a data pattern, a transmitter in communication with the data generator, the transmitter to transmit the data pattern as a test data pattern, receiver to receive the test data pattern from the transmitter, and a comparator coupled with the receiver, the comparator to compare the data pattern with the test data pattern from the receiver and to verify proper operation of a memory channel. A method includes providing a seed value to a transmit and a receive pattern generator in a memory, generating data at the transmit pattern generator from the seed value and transmitting the data from the memory, looping the data to a receiver on the memory, using the seed value to generate data with the receive pattern generator, and comparing the data from the receive pattern generator and the transmit pattern generator to determine if any errors occurred.

Abstract: In some embodiments, the inventions include a chip having a message signaled interrupt redirection table (MRT) that contains entries including an address field and a data field. The chip also includes translation circuitry to translate an address field and a data field of a message signaled interrupt (MSI) signal by copying contents of the address field and data field of an entry in the MRT into the address field and data field of the MSI. Other embodiments are described and claimed.

Abstract: In some embodiments, a chip includes clock generation circuitry to create a clock signal, and reference signal oscillator circuitry to produce a reference signal with a higher frequency than the clock signal. The chip includes a counter to change a count value in response to changes in the reference signal; and count logic circuitry to cause count storage circuitry to read the count value in response to at least some changes in the clock signal and to make at least some of the values in the count storage circuitry related to a duty cycle of the clock signal available to an external tester. Other embodiments are described and claimed.

Abstract: In some embodiments, the invention includes a chip having a register to include an operation type signal. The chip also includes control circuitry to receive a first command and in response to the first command to cause the chip to perform a first operation if the operation type signal has a first value and to cause the chip to perform a second operation if the operation type signal has a second value. The chip may be a memory chip in a memory system. Other embodiments are described and claimed.

Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The control circuitry selects an impedance level for the first and second resistive structures, and detect coupling of a remote receiver to the transmitter through interconnects and detect decoupling of the remote receiver from the transmitter. Other embodiments are described and claimed.

Abstract: A current level of power consumption of a system is monitored by a power consumption controller. When the current level of power consumption exceeds power guidelines, the power consumption controller adjusts the power consumption of one or more components in the system at a time by at least one power consumption level. Adjusting such power consumption level may have an impact on the performance of the system. Various techniques may be used to reduce (ramp down) power consumption or allow increase (ramp up) in power consumption. A power management policy may use one or combination of such techniques in order to enable the system to deliver the high performance while still maintaining the power consumption of the system within the power guidelines.

Abstract: In some embodiments, a chip includes at least four groups of memory banks and at least four groups of output conductors wherein each group of output conductors corresponds to a different one of the groups of memory banks. The chip also includes circuitry to perform a read operation by providing read data from at least one of the banks of each of the groups of memory banks to its corresponding group of output conductors. Other embodiments are described.

Abstract: In some embodiments, a chip comprises control circuitry to provide inband signals, inband output ports, and transmitters to transmit the inband signals to the inband output ports. The control circuitry selectively includes loopback initiating commands in the inband signals. Other embodiments are described and claimed.

Abstract: A cosmic ray detector includes a cantilever with a first tip. The detector also includes a second tip and circuitry to provide a signal indicative of a distance between the first and second tips being such as would be caused by a cosmic ray interaction event.

Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.

Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.

Abstract: In some embodiments, a chip includes a memory core, control circuitry, and first ports, second ports, and third ports. The first ports are to only receive signals, the second ports are to only provide signals, and the control circuitry is to control whether the third ports are to only receive signals or only provide signals. Other embodiments are described and claimed.

Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, a transmitter, change detection circuitry, and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The change detection circuitry detects changes in voltages of the first and second nodes following a change in voltage of the variable voltage source. The control circuitry determines whether the changes in voltages of the first and second nodes are consistent with the transmitter being coupled through interconnects to a remote receiver. Other embodiments are described and claimed.

Abstract: In some embodiments, a system includes a first memory assembly coupled to a first channel and a second memory assembly coupled to a second channel. The system includes a memory controller to write first and second primary data sections to the first and second memory assemblies, respectively, and write first and second redundant data sections to the second and first memory assemblies, respectively, wherein the first and second redundant data sections are redundant with respect to the first and second primary data sections, respectively. Other embodiments are described and claimed.

Abstract: In some embodiments, a memory controller includes first and second memory channel interfaces and memory access control circuitry. The memory access control circuitry is to send first and second primary data sections to the first and second memory channel interfaces, respectively, and send first and second redundant data sections to the second and first memory channel interfaces, respectively. The first and second redundant data sections are redundant with respect to the first and second primary data sections, respectively. Other embodiments are described and claimed.

Abstract: In some embodiments, the invention includes a device and bus transaction control circuitry to provide bus transactions with tag space, wherein under some conditions at least part of the tag space is used to provide debug information and under some conditions at least part of the tag space is used to represent a transaction number. Other embodiments are described and claimed.

Abstract: In some embodiments, a chip includes first and second ports to provide first and second received data signals and first and second received strobe signal, respectively. An internal clock signal has a fixed phase relationship to the first received strobe signal and the second received strobe signal has an arbitrary phase relationship with the internal clock signal. First and second write blocks latch the first and second received data signals synchronously with the first and second received strobe signals, respectively. Other embodiments are described and claimed.

Abstract: In some embodiments, a memory controller includes first and second memory channel interfaces and memory access control circuitry. The memory access control circuitry is to send first and second primary data sections to the first and second memory channel interfaces, respectively, and send first and second redundant data sections to the second and first memory channel interfaces, respectively. The first and second redundant data sections are redundant with respect to the first and second primary data sections, respectively. Other embodiments are described and claimed.