Abstract: A universal system for monitoring activities and motions during exercise and controlling the resistance provided to a user of exercise equipment during the motions. The system having at least one sensor to detect at least one of physical parameter of the exercisers activity such as force, acceleration, and/or direction of user movements. The resistance mechanism provides an adjustable and variable resistance and a dampened response to an exerciser while the sensors monitor the forces and resulting movement of the user interface. The system provides an adjustable resistance system for exercising parts of the body having complex movements over a full range of motion such as the arms, legs, neck, wrist, ankle, and torso. The present invention is also adaptable to existing fitness equipment. The system can also provide effective resistance and damping over the range of motion in free space.

Abstract: An output driver which maintains over voltage protection on individual circuit elements, providing either a level shifted logic high or a floating-state on its output. The output driver includes a latch driven by a set circuit and a reset circuit. The latch output drives an output stage which produces a level shifted logic high when the latch is set and a floating-state when the latch is reset. Minimal voltage is applied across individual circuit elements by supplying power in concurrent incremental voltage levels to the output driver.

Abstract: A process variation monitor sensing transistor parameters and supplying a compensation signal. The process variation monitor, monitors fabrication variations by utilizing a first and second transistor. The first transistor can be an un-implanted or a partially implanted transistor. The second transistor can be a conventional, fully implanted transistor or a partially implanted transistor. The second transistor having parameters which reflect process variations. The second transistor has a predetermined length, width, and implanting relationship to the first transistor. The transistors are biased which creates a signal in the first transistor that varies proportional to the parameters of the second transistor. Process induced parameters such as threshold voltage, effective length, transconductance, and mobility of the second transistor can be monitored by the first transistor, such that the signal produced by the first transistor can be used to compensate sensitive circuits for process variations.

Abstract: A CMOS compensation circuit receives compensation signals and provides a proportional compensation signal to an application circuit. The compensation circuit is implemented having a load for receiving at least one compensation signal. A device mirroring the load provides the application circuit with a compensation signal proportional to the received compensation signals. In a preferred embodiment, the compensation circuit provides a current controlled oscillator a compensation current to modify the bias of the oscillator. In a preferred embodiment, the compensation current is supplied by a fabrication variation monitor. The fabrication variation monitor supplies a signal to compensate for variations in the fabrication process, such as threshold voltage and effective length.

Abstract: A video adapter for use in multimedia computer data processing system is disclosed. The video adapter is able to perform real time video resizing, such as video downscaling and upscaling, during compression and decompression playback within the multimedia computer data processing system. The data processing system typically includes a central processing unit, an input/output bus, and a memory controller for controlling a system memory and a level 2 cache for sending or storing data from the video adapter. The video adapter includes a bus enable logic, coupled to both the video decoder, video encoder, and field memory, that performs the video upscaling and downscaling. The bus enable logic also allows a video pass-through to allow compression and decompression of full resolution images without the need for upscaling or downscaling.

Abstract: A differential input, voltage controlled current source utilizing a low supply voltage and realizing a wide common mode input range. The voltage controlled current source provides a differential output current as a function the differential input voltage which is independent of the common mode input voltage level. The voltage controlled current source includes a first and a second differential amplifier receiving the differential input voltage and producing a differential current having a first and second leg. The first leg of the differential output current is tracked by a current mirror which floats as a function of the bias voltage and common mode input voltage. A second floating current mirror tracks the second differential output current leg. The first and second current mirrors are coupled to a replica bias circuit which is connected in parallel with the differential amplifiers.

Abstract: An apparatus for utilizing multiple processors to render graphical objects for display including apparatus for storing in memory a list of pixel locations assigned to each of the processors, apparatus for scan converting each received graphical object into pixels, and each processor including apparatus for rendering graphical object pixels at pixel locations assigned to the processor. In addition, a method of utilizing multiple processors to render graphical objects for display including the steps of storing in memory a list of pixel locations assigned to each of the processors, scan converting each received graphical object into pixels, and each processor rendering graphical object pixels at pixel locations assigned to the processor.

Abstract: An application request for off-screen VRAM is satisfied transparently to the application by allocating off-screen VRAM, if available, or system RAM if off-screen VRAM is unavailable. In addition, a list is kept of previous memory requests so that requests which were satisfied by allocating system RAM can be switched to off-screen VRAM, if such off-screen VRAM should later become available. Allocation of off-screen VRAM is controlled by a device driver that responds to various application memory requests and controls the off-screen VRAM resources, among other things. The device driver receives an allocation request for off-screen VRAM and determines whether the request may be honored with available off-screen VRAM resources. If the request can be honored with available off-screen VRAM resources, the device driver allocates a portion of the available off-screen VRAM resources to honor the request and decreases the amount of available off-screen VRAM resources.