Abstract: A contact device having a plurality of nominally coplanar first contact elements makes electrical contact with corresponding nominally coplanar second contact elements of an electronic device when the contact device and the electronic device are positioned so that the plane of the first contact elements is substantially parallel to the plane of the second contact elements and relative displacement of the devices is effected in a direction substantially perpendicular to the plane of the first contact elements and the plane of the second contact elements. The contact device comprises a stiff substrate having a major portion with fingers projecting therefrom in cantilever fashion, each finger having a proximal end at which it is connected to the major portion of the substrate and an opposite distal end and there being one or two contact elements on the distal end of each finger. It is necessary to effect relative displacement of the devices by a distance d from first touchdown to achieve last touchdown.

Abstract: A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

Abstract: A contact device having a plurality of nominally coplanar first contact elements makes electrical contact with corresponding nominally coplanar second contact elements of an electronic device when the contact device and the electronic device are positioned so that the plane of the first contact elements is substantially parallel to the plane of the second contact elements and relative displacement of the devices is effected in a direction substantially perpendicular to the plane of the first contact elements and the plane of the second contact elements. The contact device comprises a stiff substrate having a major portion with fingers projecting therefrom in cantilever fashion, each finger having a proximal end at which it is connected to the major portion of the substrate and an opposite distal end and there being one or two contact elements on the distal end of each finger.

Abstract: Optical characteristic measuring systems and methods such as for determining the color or other optical characteristics of an object are disclosed. Perimeter receiver fiber optics are spaced apart from a source fiber optic and receive light from the surface of the object being measured. Light from the perimeter fiber optics pass to a variety of filters. The system utilizes the perimeter receiver fiber optics to determine information regarding the height and angle of the probe with respect to the object being measured. Under processor control, the optical characteristics measurement may be made at a predetermined height and angle. Various color spectral photometer arrangements are disclosed. Translucency, fluorescence, gloss and/or surface texture data also may be obtained. Audio feedback may be provided to guide operator use of the system. The probe may have a removable or shielded tip for contamination prevention. A method of producing prostheses based on measured data also is disclosed.

Abstract: A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

Abstract: A DRAM cell and a process for formation of a capacitor of a DRAM cell.

Abstract: A method for making semiconductor thin film transistors (TFTs) having a bottom gate such that the gate electrode is formed in a furrow of an insulating layer, with a gate oxide and body polysilicon formed thereon, thereby allowing the source and drain level to be in a smooth plane parallel with the gate level. Steps that may be included in the disclosed method for fabricating thin film transistors having a bottom gate are: a) forming an insulating layer on a substrate, and forming a furrow by etching the insulating layer at a portion corresponding to where a gate line is to be formed; b) forming a gate line in the furrow by depositing a conductive layer, and etching back the conductive layer; c) forming a gate insulator on the gate line, forming a semiconductor layer on the gate insulator; and d) forming impurity regions at opposite sides of the gate line.

Abstract: A phase shift mask and method of manufacture are disclosed in which a light shielding layer is formed on a substrate and patterned to produce parallel areas of predetermined intervals and spacings of the desired shape. A phase shift film is formed on the substrate and light shielding layer. The phase shift film is patterned so that remaining portions of the phase shift film fully shield the parallel areas of the light shielding layer.

Abstract: A mask and method of manufacturing is disclosed. The mask may include a transparent quartz substrate having light-transmitting regions and light-shielding regions, a light-control layer formed on the substrate excluding a portion corresponding to a light-transmitting region of an edge portion, and a light-shielding layer formed on the light-control layer of an light-shielding region. The method may include the steps of preparing a quartz substrate, forming a light-control layer on the quartz substrate, forming a light-shielding layer on the light-shielding region of the light-control layer, and selectively etching the light-control layer corresponding to light-transmitting regions of an edge portion of the substrate.

Abstract: A structure and fabricating method of a thin film transistor which is suitable for an SRAM memory cell. The thin film transistor structure includes: an insulation substrate; a gate electrode formed on the insulation substrate; a gate insulation film formed on the gate electrode and on the insulation substrate; a semiconductor layer formed on the gate insulation film; channel regions formed in parts of the semiconductor layer at both sides of the gate electrode; a high density first conductive type first impurity region formed in the semiconductor layer over the gate electrode; and first conductive type second impurity regions of having an LDD structure formed in parts of the semiconductor layer over the insulation substrate except under the gate electrode.

Abstract: A method and apparatus are provided for testing whether an electronic circuit, or DUT, for generating a clock signal is generating a signal of a frequency within a regulated frequency range. The method includes the steps of: supplying a driving clock or signal to cause the circuit to be tested to generate test clock signals as designed; causing a clock generator to generate an upper limit frequency clock signal and a lower limit frequency clock signal based on the clock signal of the circuit; simultaneously counting the testing clock signal of the circuit, the upper limit frequency clock signal and the lower limit frequency clock signal of the clock generator, and generating resultant signals upon the count reaching certain numbers; and issuing a pass signal when a count result of the upper limit frequency clock signals is output first, and a count result of the testing clock signal of the circuit is output next, and otherwise issuing a fail signal.

Abstract: A phase shift mask is disclosed, which includes a substrate, a plurality of first light shading film pairs formed at an interval on the substrate, a plurality of phase shift layers formed on the first light shading film pairs, and a plurality of second light shading pairs formed on portions of the substrate exposed between the first light shading film pairs. A manufacturing method of a phase shift mask also is disclosed, which includes the steps of providing a substrate, forming a plurality of first light shading film pairs at an interval on the rear side of the substrate, forming a plurality of phase shift layers on the plurality of first light shading film pairs, and forming a plurality of second light shading film pairs between the plurality of first light shading film pairs. The mask and its manufacturing methods may improve the process by addressing the difference in transmitted optical intensities resulting from the refractive indices and optical transmissivities of the various layers.

Abstract: A programmable semiconductor element having an antifuse structure and a method for fabricating the same is disclosed. The fabrication method for a programmable semiconductor element having an antifuse structure includes processes for forming a first insulation film on a silicon substrate, forming a conductive material having a fixed width on the first insulation film, forming a second insulation film on the conductive material, forming a recess by etching a part of the second insulation film, forming a conductive link at corners of the recess in the second insulation film, forming a contact hole by etching the second insulation film in the recess thereof having no conductive link formed thereon, exposing the conductive material at a lower part, forming two separated conductors by etching the exposed conductive material, and forming a capping insulation film on the overall surface of the substrate and covering the conductive link.

Abstract: A semiconductor memory cell and a process for formation thereof is disclosed. A capacitor is disposed below a transistor, so that a DRAM cell that may be suitable for a high density semiconductor device is produced. A semiconductor device according to the present invention includes: a buried capacitor consisting of a storage electrode, a dielectric layer and a plate electrode formed on a substrate in a planar form; and a transistor formed above the capacitor, a source/drain region of the transistor being connected to the storage electrode of the capacitor.

Abstract: A MOSFET in accordance with this invention includes: a metal silicide layer formed on a impurity region and on the upper surface of a gate electrode; a metal silicide nitride layer formed on the metal silicide layer; and a metal nitride layer formed on the metal silicide nitride layer. The process for formation of a conductive layer includes the steps of: (a) forming an impurity region in a semiconductor substrate; (b) forming a metal layer on the impurity region; (c) carrying out a heat treatment under an inert gas atmosphere to form a metal silicide of metastable phase; and (d) carrying out a heat treatment under an nitrogen gas atmosphere so as for the metal silicide of the metastable phase to be phase-transited to a stable phase.

Abstract: An executable program is stored in compressed form in a ROM, from which compressed program data is fetched to be expanded by an expandor to a pre-compression form. The expanded data is then decoded by an instruction decoder for execution. This novel setup reduces a memory usage amount in main storage including the ROM. If a branch instruction appears, a controller converts a pre-compression branch destination address to a corresponding post-compression branch destination address and sets a value thereof to a program counter.

Abstract: The capacitor area is increased with a cylinder-shaped first storage electrode overlapped with a second electrode in an area which covers two adjacent cells. Included in a semiconductor device using the invention may be: a semiconductor substrate; a word line on the substrate; impurity regions at opposite sides of the word line in the substrate; a first contact hole on an odd impurity region; a first storage electrode connected to the first contact hole, which is overlapped with an adjacent even cell; a first sidewall storage electrode at opposite sides of the first storage electrode; a second contact hole on the even impurity region, the second contact hole having an insulated sidewall; a second storage electrode connected to the second contact hole, which is overlapped with an adjacent odd cell; a second sidewall storage electrode at opposite sides of the second storage electrode.

Abstract: The circuit and method for detecting data collisions in a communication network, the circuit including: a data transition detecting section for receiving Manchester encoded data signals RXD, and detecting a transition at the center of the bit cell of the encoded data signals, and outputting a transition detecting signal Z having a certain pulse width; a delayer for delaying received clock signals RXC having a certain cycle synchronized with the received data signals RXD, and outputting delayed clock signals DRXC; and a data collision detecting section turning to an active mode in accordance with a data receiving status signal CRS illustrating the receiving status of the received data signals, and shifting the status of output signals in accordance with the transition detecting signal Z upon clocking of the delayed clock signal DRXC.

Abstract: A digital video memory circuit. The circuit includes a DRAM for storing thereto and reading data therefrom, a register group having registers for holding data to be written to and read from the DRAM, a selector having switching transistors connecting registers in the register group to an I/O data bus, respectively, for storing data on the I/O data bus to the DRAM and for transferring data from the DRAM to the I/O data bus. The register group includes a first register set and a second register set connected serially between the DRAM and the selector, the second register set transferring data on the I/O data bus to the first register set, and the first register set transferring data from the second register set to the DRAM. The second register set can receive data on the I/O data bus while the first register set writes previously received data to the DRAM.

Abstract: A process for packaging a solid type image pick-up device and a device produced by the packaging process. The process includes the steps of: forming a protecting layer on a light receiving region of an image pick-up chip formed on a semiconductor wafer; separating the image pick-up chip after forming the protecting layer; attaching the image pick-up chip on a lead frame and connecting leads of the lead frame to a pad of the separated image pick-up chip; sealing the chip within a chip-receiving body by molding with a resin and by using a mold having a projection, the projection extending to the protecting layer; and removing the protecting layer, and sealing a transparent plate on a cavity formed by the projection.