Abstract: A SOI MOSFET 10 may be formed from silicon single crystal as a substrate body that is formed on an embedded oxide film 11. For example, a P-type body 12, a channel section 13, and N-type source region 14 and drain region 15 are formed therein. Low concentration N-type extension regions 18, a gate electrode 17 provided through a gate dielectric layer 16 and sidewalls 19 are formed therein. A body terminal 101 in which a resistance (body resistance) Rb between itself and a body is positively increased is provided, and the body terminal 101 is connected to a source region 14. This structure realizes a SOI MOSFET with a BTS (Body-Tied-to-Source) operation accompanied by a transient capacitive coupling of a body during a circuit operation.

Abstract: Embodiments include semiconductor devices and a methods for manufacturing the same that suppress deficiencies in the transistor characteristics. A method for manufacturing a semiconductor device includes the steps of (A) forming a polishing stopper layer 14 having a predetermined pattern over a substrate 10, (B) removing a part of the substrate using the polishing stopper layer 14 as a mask to form a trench 16, (C) forming a trench oxide film 18 over a surface of the substrate 10 that forms the trench 16, (D) forming an insulating layer 21 that fills the trench 16 over an entire surface of the substrate, (E) polishing the insulating layer 21 by a chemical-mechanical polishing, (F) removing the polishing stopper layer 14, and (G) etching a part of the insulating layer 21 to form a trench insulating layer 20.

Abstract: A semiconductor device 1000 may include a protective insulation layer 50, a pad opening section 60 provided in the protective insulation layer 50, and a wiring layer which the pad opening section reaches. First and second wiring layers 30 and 32 are provided at levels below the wiring layer 40 which the pad opening section reaches. The first and second wiring layers 30 and 32 provided at levels below the wiring layer 40 which the pad opening section reaches are formed outside a region of the pad opening section 60 as viewed in a plan view.

Abstract: Certain embodiments relate to semiconductor devices having an improved dielectric strength and methods for manufacturing the same. A semiconductor device 1000 may have a field effect transistor 100. The field effect transistor 100 includes a gate dielectric layer 30, a source region 32 and a drain region 34. A first semi-recessed LOCOS layer 40 may be formed between the gate dielectric layer 30 and the drain region 34. A second semi-recessed LOCOS layer 50 may be formed between the gate dielectric layer 30 and the source region 32. A first offset impurity layer 42 may be formed below the first semi-recessed LOCOS layer 40. A second offset impurity layer 52 may be formed below the second semi-recessed LOCOS layer 50.

Abstract: Embodiments include a semiconductor device comprising: a pad formed on an insulating layer and having an electric connection region with external components; and a protective insulating layer which has an aperture for exposing the electric connection region. The protective insulating layer may include a first insulating layer and a second insulating layer, and side surfaces of these insulating layers are exposed to the aperture. At least part of the side surfaces surrounding the electric connection region have a tapered configuration at an acute angle to a top surface of the pad. This semiconductor device not only enables reduction of the fabrication steps, but also provides a reliable passivation structure for a pad with sufficient thickness and stress relaxation characteristics.

Abstract: Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The interlayer dielectric layer 20 includes at least a first silicon oxide layer 20b that is formed by a polycondensation reaction of a silicon compound and hydrogen peroxide, and a second silicon oxide layer 20c formed over the first silicon oxide layer and containing an impurity. The pad section 30A includes a wetting layer 32, an alloy layer 34 and a metal wiring layer 37.

Abstract: Semiconductor devices including a non-volatile memory transistor and methods for manufacturing such semiconductor devices are described. One semiconductor device may include a silicon substrate 10, a floating gate 22 disposed above the silicon substrate 10 through a first dielectric layer 20, a second dielectric layer 26 that contacts at least a part of the floating gate 22, a control gate 28 formed over the second dielectric layer 26, and a source region 14 and a drain region 16 formed in the silicon substrate 10. A wiring layer 40 is provided above the floating gate 22, and the entirety of the floating gate 22 is overlapped by the wiring layer 40 as viewed in a plan view.

Abstract: Certain embodiments include a semiconductor device capable of preventing a retardation of signal transmission between the smallest units, a method for the manufacture thereof, a circuit substrate and an electronic device. Embodiments also include a manufacturing method comprising a laminating step of forming tunnel insulating films 12 and 22, floating gates 14 and 24, dielectric films 16 and 26, control gates 18 and 28 on first and second memory cell areas 10 and 20 formed mutually adjacent to each other on a semiconductor substrate 30, a plurality of impurity area formation steps of forming sources and drains 32, 34, 36 and 38 on the first and second memory cell areas 10 and 20, and forming a connecting area 40 capable of forming an electric connection between one 32 of the source and drain of the first memory cell area 10 and one 36 of the source and drain of the second memory cell area 20.

Abstract: A semiconductor device in accordance with one example of the present invention pertains to a semiconductor device to be used for a CMOS inverter circuit, comprising a BOX layer 2 formed on a silicon substrate 1, a SOI film 3 including single crystal Si formed on the BOX layer, a gate oxide film 4 formed on the SOI film 3, a gate electrode 5 formed on the gate oxide film, and diffusion layers 7, 8 for source/drain regions formed in source/drain regions of the SOI film 3, wherein, when a power supply voltage of 0.6 V is used, a thickness TSOI of the SOI film 3 is 0.084 &mgr;m or greater and 0.094 &mgr;m or smaller, and an impurity concentration of the SOI film is 7.95×1017/cm3 or greater and 8.05×1017/cm3 or smaller.

Abstract: Embodiments include a semiconductor device including a well structure such that well areas can be formed with a higher density of integration and a plurality of high-voltage endurable transistors can be driven independently of one another with different voltages, and a method of manufacturing the semiconductor device. The semiconductor device may include a triple well comprising a first well formed in a silicon substrate and having a first conductivity type (P-type), a second well formed in adjacent relation to the first well and having a second conductivity type (N-type), and a third well formed in the second well and having the first conductivity type (P-type). A high-voltage endurable MOSFET is provided in each of the wells. Each MOSFET has an offset area in the corresponding well around a gate insulating layer. The offset area is formed of a low-density impurity layer which is provided under an offset LOCOS layer on the silicon substrate.

Abstract: Semiconductor devices and methods for manufacturing the same in which deterioration of the electrical characteristic is suppressed are described. One method for manufacturing a semiconductor device includes the steps of: forming a first polysilicon layer 32 on a gate dielectric layer 20; forming a silicon nitride layer 92 on the first polysilicon layer 32; forming a second polysilicon layer 94 on the silicon nitride layer 92; forming sidewall spacers; forming an insulation layer 60 that covers the second polysilicon layer 94; planarizing the insulation layer 60 until an upper surface of the second polysilicon layer 94 is exposed; removing the second polysilicon layer 94; removing the silicon nitride layer 92 to form a recessed section 80; and filling a metal layer 34 in the recessed section 80 to form a gate electrode 30 that includes at least the first polysilicon layer 32 and the metal layer 34.

Abstract: Certain embodiments of the present invention relate to a method for manufacturing a semiconductor device in which, when a cell capacitor of a DRAM and a capacitor element in an analog element region are mix-mounted on the same chip, the manufacturing steps can be simplified. First, the connection layer 19 and the bit line 300 are simultaneously formed. Next, the lower electrodes 55a and 55b of the capacitor elements 600a and 600b and the storage nodes 53a and 53b of the cell capacitors 700a and 700b are simultaneously formed. Next, a dielectric layer (ON layer 61) of the capacitor elements 600a and 600b and a dielectric layer (ON layer 61) of the cell capacitors 700a and 700b are simultaneously formed. Then, the upper electrodes 69a and 69b of the capacitor elements 600a and 600b and the cell plate 67 of the cell capacitors 700a and 700b are simultaneously formed.

Abstract: A method for manufacturing a semiconductor device that maintains good embedding property of plug metal, and expands the short margin of upper wiring layers to be connected to plugs, may include enlarging an end region 18 of a hole 12, such that embedding of a barrier metal 13 and a plug metal 14 in the hole 12 that is given a high aspect ratio is facilitated. Next, a planarization step is conducted against deposited surfaces of the plug metal 14 by a chemical mechanical polishing (CMP) process. In this step, a part of the interlayer dielectric layer 11 is removed together with an unnecessary portion of the plug metal 14 to a level where the end region (having a diameter d2) that is greater than a practical diameter d1 of the hole 12 disappears. Then, an upper wiring layer 15 is patterned, using a lithography technique, on the planarized interlayer dielectric layer 11 having an exposed portion of the plug metal 14 that has the practical diameter of the hole.

Abstract: A semiconductor device 1000 may include first and second switch elements 1000A and 1000B formed in first and second element forming regions 16a and 16b of a SOI layer 10a, respectively. The first and second switch elements 1000A and 1000B form a BiCMOS inverter circuit, and each includes a field effect transistor and a bi-polar transistor. A first p-type body region 50a is electrically connected to an n-type source region 120. The first p-type body region 50a is electrically connected to a first p-type base region 220. A second n-type body region 54a is electrically connected to a second n-type collector region 430. A p-type drain region 330 is electrically connected to a second p-type base region 420.

Abstract: Semiconductor devices and methods for manufacturing the same in which deterioration of electrical characteristics are suppressed are described. One method for manufacturing a semiconductor device includes the steps of: (a) forming a gate dielectric layer 20; (b) forming a polysilicon layer 32 having a specified pattern on the gate dielectric layer 20; (c) forming sidewall spacers 50 on side walls of the polysilicon layer 32; (d) depositing an insulation layer 62 that covers the polysilicon layer 32; (e) planarizing the insulation layer 62 until an upper surface of the polysilicon layer 32 is exposed; (f) removing a part of the polysilicon layer 32 in a manner so that at least the gate dielectric layer 20 is not exposed, to thereby form a recessed section 80 on the polysilicon layer 32; and (g) filling a metal layer 34 in the recessed section 80 to form a gate electrode that includes at least the polysilicon layer 32 and the metal layer 34.

Abstract: Embodiments include a semiconductor device including a non-volatile memory transistor with a split-gate structure that is operable at a lower voltage. The semiconductor device includes a P-type silicon substrate 10 that includes a memory region 4000, an N-type first well 11 located in the memory region 4000, and a P-type second well located in the first well 11. The semiconductor device includes a non-volatile memory transistor with a split-gate structure. A source 16 and a drain 14 of the non-volatile memory transistor are located in the second well 12. The silicon substrate 10 and the second well 12 are isolated from each other by the first well 11. Therefore, the potential of the second well 12 can be set independently of the potential of the silicon substrate 11.

Abstract: Semiconductor devices and methods for manufacturing the same in which deterioration of electrical characteristics are suppressed are described. One method for manufacturing a semiconductor device includes the steps of: forming a gate dielectric layer 20 and a silicon layer 32 on a semiconductor layer 10; forming sidewall insulation layer 62 at the sides of the silicon layer 32; forming a planarized first insulation layer 50; removing the silicon layer 32 in a manner that the gate dielectric layer 20 is not exposed, to thereby form a recessed section 80; partially filling a metal layer 34 in the recessed section 80; forming a second insulation layer 60 in a recessed section 82; etching the first insulation layer 50 to form a through hole 90a; and forming a contact layer 92a in the through hole 90a. The second insulation layer 60 and the sidewall insulation layer 62 are formed from a material different from that of the first insulation layer 50.

Abstract: Embodiments of the present invention include a method for manufacturing a semiconductor device, in which, when a DRAM and a MOS field effect transistor that becomes a component of a logic circuit are mix-mounted on the same chip, the DRAM and the MOS field effect transistor can be provided with designed performances. After a capacitor 700 of the DRAM is formed, silicide layers 19a and 19b are formed over N+ type source/drain regions 41c and 41d of MOS field effect transistors 200c, 200d and 200e that are located in peripheral circuit region 2000 and logic circuit region 3000.

Abstract: A semiconductor device may include a fuse section 110 in which a plurality of fuses 20 to be fused by irradiation of a laser beam are formed. The fuses 20 are arranged at a specified pitch. A first insulation layer 33 is embedded between adjacent ones of the fuses 20. A second insulation layer 39 is formed on the first insulation layer 33. The first insulation layer 33 and the second insulation layer 39 are formed such that their interface 42 is generally at the same level as the top surface of the fuses 20. As a result, the fuses may be reliably fused without generating cracks in the interface 42 at the time of fusing the fuses.

Abstract: A semiconductor device 1000 may include an element isolation region 14, an n-type field effect transistor 100 and an npn-type bipolar transistor 200 formed on a SOI substrate 10. A p-type body region 50a may be electrically connected to an n-type source region 120. The p-type body region 50a may be electrically connected to a p-type base region 220. An n-type drain region 130 may be electrically connected to an n-type collector region 230. An n-type source region 120 may be formed structurally isolated from an n-type emitter region 210.