Abstract: A method and apparatus for selecting a particular node from a plurality of nodes connected to a common bus to allow the node to use the bus. The nodes have a pre-determined priority. After initially enabling the nodes, the bus is monitored for a bus idle condition. It is then determined which of the nodes are enabled message nodes, which are enabled nodes that have a message to send on the bus. There is then arbitration between the enabled message nodes after the bus is in the bus idle condition for a first period of time, such that the enabled message node having the highest pre-determined priority among the enabled message nodes is disabled for arbitration purposes, and also at the same time selects a target and performs a transfer. This procedure is repeated until all the enabled message nodes have been disabled. Thereafter, all of the nodes on the bus are enabled when the bus is in the bus idle condition for a second period of time, which is longer than the first period of time.

Abstract: A computer graphics processor capable of reading from, and writing to, virtual memory. The invention provides a graphics processing unit which includes, among other things, an graphic processor in the form of an address generator which retrieves data from memory locations, and writes data to memory locations. The address generator retrieves data from memory locations memory access request directly to a memory control unit, which retrieves the contents of the memory location. Prior to issuing the request, the address generator sends the address to a virtual translation unit, which translates the virtual address to a physical address. The virtual translation/FIFO control unit also contains three translation buffers, in which are stored the most recently accessed virtual addresses, which, in many situations, enables the virtual translation/FIFO control unit to translate the virtual address using less memory accesses.