Abstract: A clocked instruction flow is managed subject to issue and fetch constraints through a plurality of instruction latches which receive instructions from selected memory locations. By checking the number of instructions fetched and issued, the fetch program counter is adjusted responsive to the status of selected state variables indicating instructions issued and fetched. The instruction latches are fully scheduled from cycle to cycle with instructions, by fetching instructions in accordance with a fetch program counter.

Abstract: A CPU architecture is provided having a user mode (User32), a plurality of exception modes (IRQ32 etc) and a system mode (System) entered via one of the exception modes. The system mode re-uses the same set of registers (16) as the user mode and yet has access to a set of privileged resources compared to the standard resources of the user mode. Interrupt of the same type are disabled when the system is already in that exception mode, but are re-enabled when the system is moved into the system mode. Branch instructions may be used in the user and system modes, but not the exception modes.

Abstract: An instruction flow control circuit controls the selection and execution of instruction signals in a microprocessor having multiple execution units that can execute plural instructions at one time. The instruction flow control circuit compares a number of signals indicating how many execution units are available with a number of signals indicating how many execution units are required. The circuit is a matrix of transmission gates which propagate signals through, or shift signals between, various signal paths for available resources, depending on the signals requesting the executing units. A number of output gates suppress the execution of instruction signals where an execution unit is requested but none are available.

Abstract: Apparatus and method for data processing includes a common data bus (4) to interconnect a bus master circuit (6) with one or more bus slave circuits (8, 10, 12). The data processing apparatus (2) is configured to support burst mode transfers in which an address word is followed by a sequence of data words relating to addresses following on from that specified by the address word. Such transfers increase the number of data words transmitted per address word that need be specified. The data bus (4) includes an address request signal line (16) by which any of the bus slave circuits (8, 10, 12) may request an address word to be transmitted in the next processing cycle rather than a data word. In this way, the bus master circuit (6) need not be specifically adapted for the bus slaves that are attached to the bus (4), since the bus slaves can themselves indicate to what extent they are able to deal with burst mode transfers.