Abstract: A system for stripping frames transmitted by a station on a token ring network is disclosed. During operation of the system, the station receives a grant of permission to transmit onto the network. In an example embodiment, the grant of permission is a token. After receipt of the grant of permission to transmit, the station transmits one or more frames onto the network. The station counts the number of frames transmitted onto the network. The count of frames transmitted onto the network is the `frame count`. Upon transmission of the frames, the station stops forwarding frames received from the network, thus removing received frames from the network. Removing received frames from the network is referred to as `stripping`. Following transmission of the information frames, the station counts the number of frames stripped from the network. The count of frames stripped from the network is the `strip count`. When the strip count equals the frame count, the station terminates stripping.

Abstract: The present invention is directed to a control flow logic device for handling data received from a bus by a bus interface, in response to a bus read transaction, and transferred to a processor. The control flow logic includes an error checker to check data received from the bus for hard errors and parity errors and an ECC generator to generate an ECC for the received data, the ECC being forced to a bad ECC when a hard error is detected by the error checker and to a good ECC in the absence of a hard error. An error signal generator is utilized to generate and transmit an error signal to the processor when there is a hard error or a parity error in the received data and a data mover transmits the received data and the ECC to the processor.

Abstract: According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device.

Abstract: According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device.

Abstract: A modular system for supporting equipment on a wall has support panels. Each panel includes a sheet having columns of keyholes, and a rear support surface lying in a plane parallel to and spaced behind the sheet. The rear support surface has keyholes near the top of the panel and fastener elements near the bottom of the panel. The fastener elements have the same spacing as the keyholes near the top of the panel. The fastener elements project from the plane of the rear support surface toward the front support surface to permit mating with keyholes near the top of another panel to be hung below it.

Abstract: In a computer graphics system, an address generator processes physical and virtual addresses using a common command set. The address generator formulates addresses as a function of distance from the origin of the desired destination area in a destination memory to the requested position in the destination area. A plurality of context drawing commands is used to define a desired context in which drawing graphics commands operate. Different parts of the context are changeable/redefinable independently of the other parts. Graphics commands have a format of multiple fields having corresponding parameters arranged in order of common use of the parameter such that fields of less commonly used parameters are at an omittable end of the format. Raster drawing commands are delimited by a beginning and end indicator to form a drawing unit. For clip list processing, a drawing unit is stored as a single occurrence in the system command buffer.

Abstract: According to the invention a battery charger for charging a plurality of batteries includes a voltage supply connected by a pair of switches to a power converter including a transformer having a primary winding and a plurality of secondary windings. Each secondary winding is coupled to a battery. Voltage is transferred from the voltage supply to the primary winding when the switches are closed and current is transferred from the secondary windings to the batteries when the switches are open. Charge control circuitry monitors the voltage of each battery and the total battery voltage and determines the amount of current to supply to the batteries. Supervisory logic monitors the current received from the secondary windings by each of the batteries and the voltage of each of the batteries to determine the charge status of each battery and the operating status of the power converter.

Abstract: A dual processor computer system includes a first processing system having a central processing unit which executes a series of data processing instructions, a data bus system for transferring data to and from the first central processing unit, a memory unit coupled to the first central processing unit, and a cross-link communications element for transferring data into and out of the first processing system. A similarly configured second processing system, operating independently of the first processing system, is also provided. The cross-link communications element associated with the second processing system is coupled to the cross-link communication element of the first processing system, for transferring data into the second processing system from the first processing system and for transferring data into the first processing system from the second computer system.

Abstract: A dual processor data processing system having interprocessor error checking includes a first central processing unit executing a series of instructions. A second central processing unit executes the same series of instructions independently of and in synchronism with the first central processing unit. A first data bus is coupled to the first central processing unit for receiving data to be input to the first central processing unit and a second data bus is coupled to the second central processing unit for receiving data to be input to the second central processing unit. Error checking devices are coupled to the first and second data busses for checking data transmitted over the first and second data busses and for detecting errors on I/O reads prior to delivery of the data to the first and second central processing units. The error checking devices include comparison means for indicating an error when the data on the first and second data busses are unequal.

Abstract: A technique for distributing updated distance vectors used in routers, which are connected by point-to-point links having datagram service. Distance vectors are used by routers to route messages over the most desirable paths, but must be continually modified as a result of update messages passed between routers, to reflect changes in network topology. Datagram service does not normally ensure that such update messages will reach other routers, but the technique of the invention uses unique sequence numbers on all information packets containing distance vector update messages, and achieves efficient and timely distribution of updated distance vector information with only a modest storage requirements. Unlike reliable service, which requires each message to be delivered exactly once and in the order sent, the invention allows subsequent update messages to be delivered to the same neighboring router even if previous messages have not yet been received and processed.

Abstract: A method of manufacturing a magnetic tachometer used to generate a signal as a function of the velocity of a transducer positioning arm in a disk drive. The tachometer is formed over a one piece plastic insert having a first and second portion separated by a central breakaway region. An armature member is disposed over each of said first and second insert portion and a flexible connector is placed on a groove cut on a surface of said plastic insert. Two coils are simultaneously wound over said first and second insert portion, respectively, and connected to the flex connection. The insert is then bent to snap the breakaway region, and the resulting two coil subassemblies are folded and fastened to spacers to form a pair of fixed parallel coils. The separation between the coil is maintained at a predetermined value by the spacers to allow a magnet, attached to a counterbalance portion of a rotary positioning arm, to move therebetween and thus to generate a voltage as a function of the velocity of the magnet.

Abstract: The present invention provides translation circuitry, which in one mode of operation acts to encode variable length data words into fixed rate data coded words for use with a communication channel, or a recording means, such as a magnetic recording medium and which in another mode of operation acts to decode the coded words to data words. The translation circuitry functions such that in an encoding operation, the second and third bits of a three-bit coded word respectively have the same binary values as the first and second bits of the data word, which the coded word represents and the second and sixth bits of a six-bit coded word respectively have the same binary values as the third and fourth bits of the data word which the coded word represents.

Abstract: The present arrangement includes a circuit to receive non-differentiated pulse signals from the read circuitry of a magnetic recording medium system. These non-differentiated pulse signals are transmitted to a circuit which averages the values of the peaks of said signals, takes a predetermined percentage of that average value and produces a peak reference signal. The peak reference signal is transmitted to a comparison circuit whereat it is compared with the non-differentiated pulse signals and if the value of the peaks of the latter signals exceed the value of the peak reference signal, the comparison circuit will provide an output signal. The non-differentiated pulse signals are also transmitted to a differentiation circuit to effect a differentiation thereof and therefrom are transmitted to a zero crossover circuit. The zero crossover circuit provides a signal with a useful rising or falling edge, whose rising and falling edges occur at the zero crossovers of the differentiated signals.

Abstract: The present invention includes a first input signal circuit to receive pulse signals from a voltage-controlled oscillator (VCO), or some other controllable pulse signal source, and a second input signal circuit to receive pulse signals from a magnetic recording medium, or some pulse signal source, with which the voltage controlled oscillator is to be put in phase synchronization. A correction signal generator circuit is connected to both the input signal circuits to provide a first correction signal in response to a pulse signal from the recording medium and to provide a second correction signal in response to a pulse signal from the VCO. There is a third circuit which monitors how long a correction signal is in effect and if such a correction signal is present for longer than a predetermined time, the third circuit terminates the correction signal to enable a new correction signal to be generated in response to the next one of said input signals to arrive.