Abstract: A split-polysilicon CMOS DRAM process incorporating self-aligned silicidation of the cell plate, transistor gates and N+ regions with a minimum of additional processing steps. By employing a light oxidation step to protect the P-channel transistor sidewall gates from silicidation during a subsequent processing step, the process avoids the problems that may be created by the double etching of the field oxide and active area regions that has heretofore been required for self-aligned silidation utilizing a split-polysilicon CMOS process. A protective nitride layer is used to prevent oxidation on those regions which are to be silicided. When this improved process is utilized for DRAM fabrication, the protective nitride layer may also be utilized as the cell dielectric.

Abstract: An improved CMOS fabrication process which uses separate masking steps to pattern N-channel and P-channel transistor gates from a single layer of conductively-doped polycrystalline silicon (poly) and incorporates self-aligned salicidation of conductive regions. The object of the improved process is to reduce the cost and improve the reliability, performance and manufacturability of CMOS devices by a process which features a dramatically reduced number of photomasking steps and which further allows self-aligned salicidation of transistor conductive regions. By processing N-channel and P-channel devices separately, the number of photomasking steps required to fabricate complete CMOS circuitry in a single-polysilicon-layer or single-metal layer process can be reduced from eleven to eight. Starting with a substrate of P-type material, N-channel devices are formed first, with unetched poly left in the future P-channel regions until N-channel processing is complete.