Abstract: The present invention provides methods for fabricating integrated circuit structures for use in semiconductor wafer fabrication techniques. A Cu diffusion barrier/Cu seed sandwich layer is deposited on a substrate. A first sacrificial layer, deposited on the sandwich layer, is developed to form a cavity. A first Cu layer is selectively deposited on the sandwich layer inside the cavity. A second sacrificial layer is deposited on the first sacrificial layer and on the first Cu layer. A cavity is formed in the second sacrificial layer, exposing at least a portion of the first Cu layer. A second Cu layer is selectively deposited in the second sacrificial layer cavity including the exposed portion of the first Cu layer. The combination of the first and second Cu layers forms a Cu component. Subsequently, the first and second sacrificial layers are removed resulting in a Cu component that is free standing on the sandwich layer, such that the top and sides of the component are exposed.

Abstract: The present invention provides methods and systems for accessing a network URL through a pre-assigned simplified network address, correlating to the URL, and for displaying the home page having the URL as its address. These methods and systems provide easier URL and home page access because persons wanting to access the home page need only input the simplified network address, thereby avoiding the need to know and input the URL character string. The simplified network addresses of the present invention include numbers. Methods are provided for selecting numbers for assignment to URLs.

Abstract: The present invention provides a semiconductor processing device (800) including a tool (802) having one or more sensors, a primary data communication port (804) and a secondary data communication port (806). A sensor data acquisition subsystem (808) acquires sensor data from the tool via the secondary port (806). The data acquisition subsystem (808) acquires MES operation messages via the primary port (804). Sensor data are communicated to a sensor processing unit (828) of a sensor data processing subsystem (810). The sensor processing unit (828) processes and analyzes the sensor data. Additionally, the processing unit (828) can be adapted for making product or processing related decisions, for example activating an alarm if the process is not operating within control limits.

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein triple damascene structures are formed in five consecutive dielectric layers (312, 314, 316, 318 and 320), using two etching sequences. A first etching sequence comprising: depositing a first etch mask layer (322), on the fifth (top) layer (320), developing a power line trench pattern (324) and a via pattern (326) in the first mask layer, simultaneously etching the power line trench pattern (324) and the via pattern (326) through the top three dielectric layers (316, 318, 320), and removing the first etch mask layer.

Abstract: The present invention provides a novel etching technique for etching a layer of C-doped silicon oxide, such as a partially oxidized organo silane material. This technique, employing CH2F2/Ar chemistry at low bias and low to intermediate pressure, provides high etch selectivity to silicon oxide and improved selectivity to organic photoresist. Structures including a layer of partially oxidized organo silane material (1004) deposited on a layer of silicon oxide (1002) were etched according to the novel technique, forming relatively narrow trenches (1010, 1012, 1014, 1016, 1030, 1032, 1034 and 1036) and wider trenches (1020, 1022, 1040 and 1042). The technique is also suitable for forming dual damascene structures (1152, 1154 and 1156). In additional embodiments, manufacturing systems (1410) are provided for fabricating IC structures of the present invention. These systems include a controller (1400) that is adapted for interacting with a plurality of fabricating stations (1420, 1422, 1424, 1426 and 1428).

Abstract: The present invention provides a DBD cell (500) including ring shaped electrodes (512 and 514) that are positioned side-by-side on a dielectric tube (516). An AC power supply (518) is provided such that the cell and the power supply form a DBD treatment device (540) for abatement of noxious gases for example FCs that can be discharged from semiconductor fabricating devices. Additionally, one or more sensors (822) and/or one or more gas addition ports (816) can be included in a DBD cell (800) of the present invention. Several DBD cells (1030, 1036 and 1042) of the present invention can be combined to form a DBD reactor (1010) of the present invention. AC power supplies (1012, 1014 and 1016) are utilized to energize the cells (1030, 1036 and 1042).

Abstract: The present invention provides novel etching techniques for etching Si—Ge, employing SF6/fluorocarbon etch chemistries at a low bias power. These plasma conditions are highly selective to organic photoresist. The techniques of the present invention are suitable for fabricating optically smooth Si—Ge surfaces. A cavity was etched in a layer of a first Si—Ge composition using SF6/C4F8 etch chemistry at low bias power. The cavity was then filled with a second Si—Ge composition having a higher refractive index than the first Si—Ge composition. A waveguide was subsequently fabricated by depositing a cladding layer on the second Si—Ge composition that was formed in the cavity. In a further embodiment a cluster tool is employed for executing processing steps of the present invention inside the vacuum environment of the cluster tool. In an additional embodiment a manufacturing system is provided for fabricating waveguides of the present invention.

Abstract: The present invention provides tie-down devices and techniques for securing an object to a structure. The tie-down devices are formed using helix shaped elongate members including multiple coils having substantially the same dimensions and configuration. A double helix elongate member connection is prepared by securing one segment of the elongate member upon another segment. An elongate member can be utilized to secure an object to a structure by stretching the elongate member across the object, and then tying the elongate member to the structure by forming one or more elongate member connections without using fastening elements such as hooks. Separate elongate members can be joined by means of the elongate member connections provided that the elongate members include coils having substantially the same dimensions and configuration. Side surfaces of elongate member coils can be provided with a slip resistant surface.

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures are formed which compensate for misalignment between the via pattern and the trench pattern by widening the trench at the point where the misalignment has occurred. Methods and devices are also provided wherein the trench width is not affected by misalignment thus preventing electrical shorts between closely spaced interconnect lines, this technique results in a reduction of the width of the via. These dual damascene structures utilize two dielectric layers (210 and 216) having similar etching characteristics. Additionally, a hard mask layer (218) and an etch stop layer (214) having similar etching characteristics are used in these structures. In additional embodiments, manufacturing systems (610) are provided for fabricating IC structures. These systems include a controller (600) for interacting with a plurality of fabrication stations (620, 622, 624, 626, 628, 630 and 632).

Abstract: The present invention provides a manufacturing environment (110) for a wafer fab, and an SPC environment (112) for setting control limits and acquiring metrology data of production runs. A computation environment (114) processes the SPC data, which are then analyzed in an analysis environment (116). An MES environment (118) evaluates the analysis and automatically executes a process intervention if the process is outside the control limits. Additionally, the present invention provides for an electrical power management system, a spare parts inventory and scheduling system and a wafer fab efficiency system. These systems employ algorithms (735, 1135 and 1335).

Abstract: The present invention provides a manufacturing environment (210) for a wafer fab, and an SPDA data environment (212) for acquiring processing parameters and metrology data of production runs. A computation environment (214) processes the SPDA data to prepare delta graphs (536, 540 and 542) of the present invention. These delta graphs are then analyzed in an analysis environment (216). An MES environment (218) evaluates the analysis and executes a process intervention if the results of the analysis indicate processing or product quality problems in the process run of the manufacturing environment (210). Additionally, the invention provides for SPDA delta graphs of SPC control charts as well as SPC techniques utilizing process control limits based on delta graphs to identify, analyze and trouble-shoot semiconductor processing problems, in order to improve equipment reliability and wafer yield.

Abstract: The present invention provides devices for positioning frame members for fabricating a wood frame. Each device includes an elongated flexible member and wood blocks that are removably attached to the flexible member. The length of the wood blocks equals the required distance between the frame members. The blocks are separated by slots wherein the frame members are snugly fitted in order to properly position the frame members for fabricating a wood frame structure. The wood blocks can be removed from the device for subsequent use in frame structures, thus reducing lumber waste.

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures (332 and 334) are formed in consecutive dielectric layers (314 and 316) having dissimilar etching characteristics. The present invention also provides for such methods and devices wherein these dielectric layers have different dielectric constants. Additional embodiments of the present invention include the use of single layer masks, such as silicon-based photosensitive materials which form a hard mask (622) upon exposure to radiation. In additional embodiments, manufacturing systems (710) are provided for fabricating IC structures. These systems include a controller (700) which is adapted for interacting with a plurality of fabrication stations (720, 722, 724, 726, 728 and 730).

Abstract: The present invention provides a manufacturing environment (110) for a wafer fab, and an SPC environment (112) for setting control limits and acquiring metrology data of production runs. A computation environment (114) processes the SPC data, which are then analyzed in an analysis environment (116). An MES environment (118) evaluates the analysis and automatically executes a process intervention if the process is outside the control limits. Additionally, the present invention provides for an electrical power management system, a spare parts inventory and scheduling system and a wafer fab efficiency system. These systems employ algorithms (735, 1135 and 1335).

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein triple damascene structures are formed in five consecutive dielectric layers (312, 314, 316, 318 and 320), using two etching sequences. A first etching sequence comprising: depositing a first etch mask layer (322), on the fifth (top) layer (320), developing a power line trench pattern (324) and a via pattern (326) in the first mask layer, simultaneously etching the power line trench pattern (324) and the via pattern (326) through the top three dielectric layers (316, 318, 320), and removing the first etch mask layer.

Abstract: The present invention provides techniques for processing effluent gases from vacuum fabrication processes. The effluent gases are condensed on cold surfaces (512 and 514) inside a novel pump (220) resulting in a high vacuum. The pump (220) can be connected to a vacuum fabrication processing chamber (210) and to a turbo molecular pump (275). The condensate which is formed on the cold surfaces of the pump (220) is subsequently evaporated to form regenerated gases during the regeneration of the pump. A pressure vessel (280) is removably connected to the pump during regeneration, causing the regenerated gases to fill the pump and the pressure vessel at pressures ranging from about 10,343 torr (200 psi) to about 103,430 torr ( 2,000 psi). The pressure vessel is closed when substantially all condensate has evaporated. The vessel containing regenerated gases can then be connected to an on-site or to a remote gas treatment facility for removal of noxious substances.

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures are formed which compensate for misalignment between the via pattern and the trench pattern by widening the trench at the point where the misalignment has occurred. Methods and devices are also provided wherein the trench width is not affected by misalignment thus preventing electrical shorts between closely spaced interconnect lines, this technique results in a reduction of the width of the via. These dual damascene structures utilize two dielectric layers (210 and 216) having similar etching characteristics. Additionally, a hard mask layer (218) and an etch stop layer (214) having similar etching characteristics are used in these structures such that the etching characteristics of the dielectric layers are dissimilar to the etching characteristics of the hard mask and the etch stop layer. A trench (224) is formed in the hard mask layer (218).

Abstract: The present invention provides methods and systems for accessing a network URL through a pre-assigned simplified network address, correlating to the URL, and for displaying the home page having the URL as its address. These methods and systems provide easier URL and home page access because persons wanting to access the home page need only input the simplified network address, thereby avoiding the need to know and input the URL character string. The simplified network addresses of the present invention include numbers. Methods are provided for selecting numbers for assignment to URLs.

Abstract: The present invention provides devices and methods for positioning and securing medical tubes in a patient's mouth or nose. These devices have frame portions which include an inverted U-shaped portion having an upper jaw portion, two cheek portions and a lower jaw portion. Fasteners are provided to fasten the devices of the current invention on a patient's head. Medical tubes can be inserted in these devices and intubated in a patient's mouth or nose. The medical tubes can be affixed to the frame portions of the devices of the present invention.

Abstract: 058315250 The present invention provides for removable cartridge devices including removable cartridges having fan assisted cooling for housing data storage devices and brackets adapted for removably mounting the cartridges. Various features of these cartridge systems include temperature dependent fan speed control, fan failure alarms, data storage device identification number LED display and air filtration systems. Methods are provided for removably mounting these cartridges in a computer.