Abstract: A CPU and a CPU cache memory unit is coupled to a system memory bus. A graphics processor with a graphics cache memory unit is also coupled to the system memory bus as a peer. The graphics processor and the graphics cache memory unit have the same priority as the CPU to access main memory. The graphics processor and the graphics cache unit retrieve input data from main memory and store this input data in a high-speed memory in the graphics cache unit. Data that represents a three-dimensional array is stored in the high-speed memory in the graphics cache unit in spatially contiguous blocks. This data may be first arranged into spatially contiguous blocks while it is still in main memory. Then, when a cache line is retrieved by the graphics cache unit, it will be stored in the high-speed memory in a spatially contiguous block.