Abstract: A low-gain, low-jitter VCO circuit implemented in CMOS provides center frequency adjustment to overcome process variations. Further, noise immunity is improved by using a separate feedback loop to provide the nominal current biasing for the oscillator chain. This feedback loop coarsely sets the center frequency. The actual control of the oscillation frequency is achieved by a second current source, whose output is added to the nominal bias current to provide a total bias to the oscillator. This second current source "fine tunes" the oscillator frequency responsive to a control signal. Because two separate current sources are used, the circuit can realize a high oscillation frequency with a low VCO gain. Another feature provides for adjusting the center frequency in response to a digital input word provided via external pins, or from internal logic or memory. The center frequency thus can be calibrated by measurement at the time of manufacture, or changes later by the end user or by other circuitry.

Abstract: A semiconductor manufacturing method is directed to forming a ferroelectric film, and in particular a ferroelectric film of the bismuth layer structure type, that has a significant component of reversible polarization perpendicular to the plane of the electrodes. The manufacturing method is conducted at low temperatures on commercially suitable electrodes and is compatible with conventional CMOS fabrication techniques. A ferroelectric strontium-bismuth-tantalate ("SBT") film is formed using two sputtering targets. A first sputtering target is comprised primarily of bismuth oxide (Bi.sub.2 O.sub.3) and a second sputtering target is comprised primarily of SBT. An initial layer of bismuth oxide is formed on the bottom electrode of a ferroelectric capacitor stack. The initial layer of bismuth oxide is directly followed by a sputtered layer of SBT.

Abstract: An analog input signal to a digital oscilloscope is sampled and digitized to form a representative waveform data sequence. A waveform is then displayed on a screen of the oscilloscope to represent the magnitude of the waveform as a function of time as indicated by the waveform data sequence. The waveform is formed by a set of vectors, each vector comprising a straight line between two points on the screen at elevations representing magnitudes of two successive input signal samples, and at horizontal positions representing timing of the two samples. The screen provides a display organized into an array of pixels, each of which may be illuminated with variable intensity, and each vector is represented by illuminating pixels having center points bounding the trajectory of the vector on the screen. The intensity of each such illuminated pixel is modulated in accordance with the distance between the pixel and the vector trajectory.

Abstract: A semiconductor manufacturing method is directed to forming a ferroelectric film, and in particular a ferroelectric film of the bismuth layer structure type, that has a significant component of reversible polarization perpendicular to the plane of the electrodes. The manufacturing method is conducted at low temperatures on commercially suitable electrodes and is compatible with conventional CMOS fabrication techniques. A ferroelectric strontium-bismuth-tantalate ("SBT") film is formed using two sputtering targets. A first sputtering target is comprised primarily of bismuth oxide (Bi.sub.2 O.sub.3) and a second sputtering target is comprised primarily of SBT. An initial layer of bismuth oxide is formed on the bottom electrode of a ferroelectric capacitor stack. The initial layer of bismuth oxide is directly followed by a sputtered layer of SBT.

Abstract: The disclosed HBT IC process can fabricate npn heterojunction bipolar transistors, Schottky diodes, MIM capacitors, spiral inductors, and NiCr resistors. Two levels of interconnect metal are available. The first level metal is a conventional dielectric-insulated metal conductor. The second level metal includes an air-bridge for contacting the HBT emitters, which are on top of three level mesa structures. It is also an advanced low loss, low capacitance, air dielectric conductor useful for long interconnects and inductors. MIM capacitors are formed by sandwiching silicon nitride between the first layer metal and a capacitor top plate made with landed air-bridge metal. Precision thin film resistors are fabricated by depositing NiCr on silicon nitride. The three-level active mesa structure is etched down to the GaAs substrate, for lateral device isolation, with a truncated pyramidal shape which permits good step coverage of dielectric and metallization layers. The wet etching process uses a composition of H.sub.

Abstract: A computer terminal keyboard is sealed by a molded elastomeric top cover, shaped to conform to the housing and keys of the keyboard, and a bottom cover shaped to enclose the base of and secure the top cover around its periphery to the keyboard housing. The top cover is shaped to provide a substantially planar surface on the top plate with elevated individual key covers integrally formed in the top cover. Portitons of the top cover extending over the top face and sides of the keyboard housing are formed in a first thickness sufficient to provide a durable covering. Portions of the top cover immediately adjacent and between the individual key covers, and the sides of the key covers, are formed in a reduced, second thickness to allow for flexure as the keys are depressed. The top surface of the top cover is planar so that spilled liquid and debris are easily wiped or brushed away from around and between the key covers.

Abstract: A high performance graphics display system for use as an engineering workstation includes a compact method of generating vectors and transmitting addresses for same from a picture processor to frame buffer control circuitry for writing or reading pixel values along the vector in the frame buffer. The system uses a multiplexed address/data bus. Off-screen memory in communication with the picture processor is used to store pixel data read along vectors in the frame buffer preceding writing a vector so that the original data can be restored when the written vector is moved or removed. Vectors are encoded by the picture processor as a first word containing the address of the beginning point of the vector and major axis and X and Y direction bits to indicate the vector's direction. A second word includes a minor axis bit, indicating whether the next pixel to be written or read is on or off the major axis, in the direction indicated for such axis in the first word.

Abstract: Computer-controlled test and measurement systems, including resources having multiple states and resources having multiple inputs, are modeled as data flow diagrams of topologically interconnected resources. A set of "tasks" are defined for changing the states of multiple-state resources and causing software resources to produce output data. Methods and apparatus, including internal and external task ordering rules, are provided to automatically interleave such tasks and implement input-ordering restrictions. Thereby, a sequence of tasks is produced to control the systems so as to assure valid data collection and protect physical resources from abuse. Data structures are illustrated for implementing the invention in an object-oriented programming environment.

Abstract: A self-contained laser module assembly has a diode laser and driver circuit enclosed with a cylindrical metal housing which forms a first electrical contact for inputting a DC voltage to power the circuit and laser. The housing has a first end which includes a lens positioned to emit a collimated laser beam along an axis of the housing and a second end including a second external electrical contact positioned to contact the power supply. One application of the module is in a pen-like pointer. The pointer includes conductive cap and body portions which are threaded together to house a laser module and a battery in end-to-end relationship. An O-ring between the battery and the body or module is axially compressed by tightening the cap on the body to enable turning on the pointer. The cap has a pocket clip through which electrical contact is selectably made between the body and a side contact on the module to cause a beam to be emitted.

Abstract: A method and apparatus are provided for mounting a laser diode in an existing TO-5 structure within a cylindrical heat sink so that the laser beam can be focused, aimed and collimated in a mechanically repeatable manner in about 45 seconds. The basis for so doing lies in the use of an alignment apparatus to align the beam of a laser diode within its TO-5 heat sink structure with a lens that has been placed within a second heat sink, and thereby to form an aimed laser optic system (ALOS). The apparatus is constructed using processes that leave several compressive forces acting within itself, whereby the structure is constrained to adopt configurations that are essentially identical upon each installation of a laser diode. An interference fit of the TO-5 heat sink flange against the second heat sink provides an additional degree of heat sinking, thereby permitting the diode to be operated at temperatures of up to 130 deg. F. without damage.

Abstract: A variable FET attenuator uses feedback in a control loop to correct the attenuator automatically for input/output return loss as the attenuator is varied with a control signal input. Both the series and shunt variable FETs are set to the proper conductance to maintain a proper input match with a desired attenuation value. A second, reference attenuator circuit provides feedback control of the primary attenuator circuit through an operational amplifier. The reference circuit is designed to be electrically equivalent to the attenuator circuit in terms of characteristic impedance. The control nodes, and attenuation control signal input and an output from the operational amplifier, are paralleled so that both the reference and primary attenuator circuits behave identically, without having to RF decouple the feedback loop from the attenuator circuit. Preferably, identical bridged-T variable attenuators are used for both the attenuator circuit and the reference circuit.

Abstract: A circular scan streak tube system for recording fast optical data includes a target having a first array of detection elements and a second array of corresponding storage elements. Changes in the scanning electron beam current representing optical events are detected and stored in the first array. The first and second arrays are segmented into two halves for continuous operation. Data stored in one half of the first array are transferred into the corresponding storage elements while data are written into the other half of the first array. Data stored in the first array are transferred in parallel to the second array. After a triggering event, the data are shifted circumferentially through the second array for output as serial data. The target is formed in a unitary planar semiconductor substrate having a buried channel for storing and conducting electric charge representing the stored data.

Abstract: A mixed bipolar-CMOS self-aligned process and integrated circuit provide a high performance NPN bipolar transistor in parallel to fabrication of a PMOSFET and an NMOSFET. Gate and base contacts are formed in a first polysilicon layer. The base contacts are implanted with P+ ion concentrations for diffusing base contact regions of the substrate in a later drive-in step. Source and drain contacts and emitter contacts are formed in a second polysilicon layer. The source and drain contacts are formed as a unit and then separated into discrete contacts by a spin-on polymer planarization and etch-back procedure. Lightly-doped lateral margins of the source, drain and base regions are ion-implanted in an initial low concentration (e.g. about 10.sup.13 atoms/cm.sup.2). The gate and base contact structures serve as a mask to self-align the implants. Then, the gate and base structures are enclosed in an oxide box having sidewalls.

Abstract: A block diagram editor system and method is implemented in a computer workstation that includes a Cathode Ray Tube (CRT) and a mouse, graphics and windowing software, and an external communications interface for test instruments. The computer is programmed for constructing, interconnecting and displaying block diagrams of functional elements on the CRT. From prestored routines for each functional element, the software assembles and executes a program that emulates the functional operations of each element and transfers data from output from each element in turn to an input of a succeeding block, as determined by the block diagram configuration. The block functions include signal generating and analysis functions, and functions for control of various types of test instruments, which can be interactively controlled through the CRT and mouse. The computer converts desired outputs of the instruments into control settings and receives, analyzes and displays data from the instruments.

Abstract: A signal viewing instrumentation control system includes a programmable test instrument, a computer having an input keyboard and/or mouse, a CRT display and a communications interface for the computer to communicate with the test instrument. The test instrument can be a digitizer, a spectrum analyzer, a power supply or a signal generator. The system includes software for the user to interactively control the test instrument through the computer. The software includes a functional characterization of the test instrument for inversely transforming a generic output for the instrument into a generalized set of control setting commands for controlling operation of the instrument. The user can graphically enter into the computer a user-specified output for the instrument. The computer converts the graphically-specified output into a specific set of the control setting commands and transmits the specific commands to the test instrument to control its operation.

Abstract: A color graphic display system has self-test capability for testing system elements between the frame buffer and the display monitor inputs. The DAC output analog signals are converted to a digital signal and processed to provide an output test bit, which is input to the graphics processor. Additional self-test hardware includes address and data lines from the graphics processor to the color map for directly loading test bit patterns into the color map. The system self-tests the frame buffer, shift registers and DACs by loading various predetermined test bit patterns into the frame buffer and the color map; cycling that data through the display system; reading the test bit; comparing the output test bit values to expected values; and reporting any errors detected. The system also includes a method for self-testing the refresh counter address path into the frame buffer.

Abstract: In a color graphics display system, video analog self-test hardware for testing the system elements between the frame buffer and the CRT display monitor is provided including a bi-directional data bus between the graphics processor and the color map, an analog comparator, an integrator, and an analog multiplexor. The self-test method includes calibrating the self-test circuitry with respect to a reference voltage. The method next includes testing the DACs by outputting predetermined bit patterns to each of the DACs via the frame buffer, measuring each DAC output level in response to each input bit pattern, comparing the DAC output levels to predetermined limits, and reporting the results. Provision is made also for testing the system clock.

Abstract: A high-speed, supply independent level shifter is implemented in bipolar, JFET, MOSFET or MESFET integrated circuit technology. A level shift circuit having a desired input potential V.sub.1 and a required output potential V.sub.2, is incorporated into a first current leg connected between first and second supply voltages. A second current leg in parallel with the first leg establishes a reference current. The two current legs are coupled by a current mirror to establish a fixed, preferably equal, relationship between the currents in the two legs. Each current leg includes a reference resistor. A buffered, floating voltage source is coupled in series with the resistor in the first leg to the control conductor of the current mirror. The voltage source is designed and the resistor values selected to provide a potential V.sub.3 that is an additive function of potentials V.sub.1 and V.sub.2 such that V.sub.1 is independent of the supply voltages.

Abstract: In an integrated circuit, a reference voltage proportional to the pinchoff voltage of a field effect transistor is created by providing a current source, including a first depletion-mode FET, and a second depletion mode FET having a source connected to the drain of the first FET at an output node. The first and second FETs have their source and drain, respectively, connected to the first and second supply voltages, respectively, so that in operation, substantially equal currents flow through the two transistors. The FETs are biased to operate in saturation. Regarding the first FET, this current is equal to I.sub.DSS (defined as I.sub.D when V.sub.GS =0) of the first FET (I.sub.DSS1) and is not greater than, and usually less than, I.sub.DSS of the second FET (I.sub.DSS2). The dimensions of the FETs are proportioned such that the gate-source voltage across the second FET substantially equals a constant times the pinchoff voltage.

Abstract: A multi-layer metallization method and structure that permits the use of sodium-ion contaminated titanium-tungsten (Ti:W) as a barrier metal with gold conductor metal on a silicon substrate, without significant degradation of device characteristics. After depositing the barrier and conductor metal layers, a layer of phosphorous-silicate glass (PSG) is anisotropically-etched to expose the field oxide and top surface of the conductor metal but leave PSG layer on each sidewall of the metallization structure. The circuit is then annealed at 400.degree. C. for 30 minutes. Then, an adhesion layer (Si.sub.3 N.sub.4) and an insulative layer (SiO.sub.2) are deposited over the metallization structure and field oxide, with the adhesion layer in contact with the top surface of the conductor metal and the gettering composition.