Abstract: A color graphic display system has self-test capability for testing system elements between the frame buffer and the display monitor inputs. The DAC output analog signals are converted to a digital signal and processed to provide an output test bit, which is input to the graphics processor. Additional self-test hardware includes address and data lines from the graphics processor to the color map for directly loading test bit patterns into the color map. The system self-tests the frame buffer, shift registers and DACs by loading various predetermined test bit patterns into the frame buffer and the color map; cycling that data through the display system; reading the test bit; comparing the output test bit values to expected values; and reporting any errors detected. The system also includes a method for self-testing the refresh counter address path into the frame buffer.

Abstract: In a color graphics display system, video analog self-test hardware for testing the system elements between the frame buffer and the CRT display monitor is provided including a bi-directional data bus between the graphics processor and the color map, an analog comparator, an integrator, and an analog multiplexor. The self-test method includes calibrating the self-test circuitry with respect to a reference voltage. The method next includes testing the DACs by outputting predetermined bit patterns to each of the DACs via the frame buffer, measuring each DAC output level in response to each input bit pattern, comparing the DAC output levels to predetermined limits, and reporting the results. Provision is made also for testing the system clock.

Abstract: A high-speed, supply independent level shifter is implemented in bipolar, JFET, MOSFET or MESFET integrated circuit technology. A level shift circuit having a desired input potential V.sub.1 and a required output potential V.sub.2, is incorporated into a first current leg connected between first and second supply voltages. A second current leg in parallel with the first leg establishes a reference current. The two current legs are coupled by a current mirror to establish a fixed, preferably equal, relationship between the currents in the two legs. Each current leg includes a reference resistor. A buffered, floating voltage source is coupled in series with the resistor in the first leg to the control conductor of the current mirror. The voltage source is designed and the resistor values selected to provide a potential V.sub.3 that is an additive function of potentials V.sub.1 and V.sub.2 such that V.sub.1 is independent of the supply voltages.

Abstract: In an integrated circuit, a reference voltage proportional to the pinchoff voltage of a field effect transistor is created by providing a current source, including a first depletion-mode FET, and a second depletion mode FET having a source connected to the drain of the first FET at an output node. The first and second FETs have their source and drain, respectively, connected to the first and second supply voltages, respectively, so that in operation, substantially equal currents flow through the two transistors. The FETs are biased to operate in saturation. Regarding the first FET, this current is equal to I.sub.DSS (defined as I.sub.D when V.sub.GS =0) of the first FET (I.sub.DSS1) and is not greater than, and usually less than, I.sub.DSS of the second FET (I.sub.DSS2). The dimensions of the FETs are proportioned such that the gate-source voltage across the second FET substantially equals a constant times the pinchoff voltage.

Abstract: A multi-layer metallization method and structure that permits the use of sodium-ion contaminated titanium-tungsten (Ti:W) as a barrier metal with gold conductor metal on a silicon substrate, without significant degradation of device characteristics. After depositing the barrier and conductor metal layers, a layer of phosphorous-silicate glass (PSG) is anisotropically-etched to expose the field oxide and top surface of the conductor metal but leave PSG layer on each sidewall of the metallization structure. The circuit is then annealed at 400.degree. C. for 30 minutes. Then, an adhesion layer (Si.sub.3 N.sub.4) and an insulative layer (SiO.sub.2) are deposited over the metallization structure and field oxide, with the adhesion layer in contact with the top surface of the conductor metal and the gettering composition.

Abstract: A process for two layer gold integrated circuit metallization is disclosed. The process includes electrodeposition of a first metal layer, preferably of gold, atop a barrier layer, followed by electrodeposition of a second metal layer or cap, atop the gold to form a first metallization layer. The cap is corrosion-resistant metal having a rigidity at annealing temperature greater than that of gold. Following annealing, a dielectric interlayer is deposited so as to fill the regions adjacent sidewalls of the first metallization layer. Vias are formed in the interlayer dielectric, a second barrier layer is deposited and photoresist is applied and patterned for electrodeposition of a second, gold metallization layer. During annealing, the rhodium cap retains the as-deposited shape of the gold in the first metallization layer to facilitate insulative spacing between the first and second metallizations and to insure complete filling of interlayer dielectric on the lower edges of the first metallization.

Abstract: In a GaAs integrated circuit, a voltage reference generator includes a pair of Schottky diodes and a first, current-source connected, depletion-mode MESFET coupled in series to conduct current from a ground node to a voltage supply node. The current-source connected FET causes a constant current to flow from the ground node through the diodes, producing a constant voltage drop which generates a constant reference voltage at a reference node between the diodes and FET. A second pair of Schottky diodes is connected in series between the source of the FET and the voltage supply node, in a loop coupling the source to the gate of the FET, to provide a voltage difference Vgs across the FET proportional to voltage drop across the second pair of diodes. This voltage difference varies with fabrication process and temperature variations and causes the first FET to modify the amount of current flow to compensate so as to maintain a constant voltage drop across the first pair of diodes.

Abstract: A self aligned, nonoverlapping gate structure for a charge coupled device is fabricated by depositing three sets of interleaved polysilicon gate electrodes. The first set of electrodes is applied in a planar form and sized to a width of about one-third the spacing of the electrodes of the first set. The second and third sets of electrodes are applied to overlap, in turn, portions of the previously applied electrodes. A thick shield layer of SiO.sub.2 is deposited and patterned atop the first and second sets of gate electrodes. After deposition of the third set of electrodes, the shield layers are removed to provide passageways extending beneath the overlapping portions of the second and third sets of electrodes. Such overlapping portions are then removed by etching through the passageways, to produce a nonoverlapping, generally planar gate structure.

Abstract: An integrated circuit gate process and structure are disclosed which provide a self-aligned, recessed gate enhancement-mode GaAsFET. The process includes making self-aligned implants prior to gate metallization, with an intermediate step of applying patches of plasma- and chemical-etch resistant dielectric, such as zirconium oxide (ZrO), over the self-aligned implants to fixedly define gate length. The self-aligned gate process includes stair-stepping three successive implants, in respect to both depth and concentration, to provide a dopant concentration gradient inclined depthwise away from each side of the gate. The self-aligned, recessed gate GaAsFET exhibits improved source-gate resistance without degradation of gate-drain capacitance, increased gain and drain-source current, and reduced knee-voltage. Gate length is minimized to the limits of photolithography without degrading input resistance.

Abstract: A self-aligned gate GaAsFET fabrication process and structure are disclosed in which the gate metallization is offset to one side of the channel aligned with the source-side implant. The arrangement is advantageously provided by a photolithographic fabrication process in which a pair of self-aligned implants are made, before gate metallization. As an intermediate step, a first etch-resistant ZrO patch is deposited over at least one of the self-aligned implants aligned therewith. Then, a second such patch is deposited which overlaps the other self-aligned implant and extend a distance over the channel between the two implants. The first and second patches are thereby spaced closer together (e.g., 0.5 .mu.m) than the implants (e.g., 1.0 .mu.m). The patches fix the gate length at less than implant spacing and offset the gate metallization along the source-side self-aligned implant, away from the drain implant. The gate is preferably recessed.

Abstract: A unit is described for use in a multi-unit decorative or structural arrangement. Each unit has, on at least one surface, an asymmetrical design which may be two dimensional or three dimensional. These asymmetrical designs are arranged to permit a number of identical units to be arranged together to form a large variety of overall designs whose final form depends upon the relative positions of the individual units within the arrangement. For example, a number of identical square tiles are provided, each having the same design and with the design created so that a tile wall can be formed from the identical tiles with hundreds of different overall designs. The same large number of overall designs may be formed from units other than square units including three dimensional building blocks and similar basic decorative or construction units.

Abstract: An insole of moisture absorbent material is shaped to conform to an average persons's foot sole so that it covers all or at least the forward portion of the wearer's foot. This insole is removably inserted in the wearer's sock to absorb moisture thereby protecting the wearer against the problems which stem from excess foot moisture and wet socks. The improved result is a washable and easily applied means for moisture protection of the wearer's feet consisting of a regular sock and a moisture absorbing insole positioned within the sock.

Abstract: A method and apparatus are described for automatically checking envelopes for objects which would interere with an automatic postal mail sorting operation. The envelopes are moved between inflated rollers and changes in the roller pressures caused by objectionable objects in the envelopes are detected to control an envelope diversion gate.

Abstract: An improved spray dryer is disclosed for drying heat sensitive food products under sanitary conditions with a maximum product recovery for a minimal dryer size. The dryer has an air flow system for moving air through a drying chamber at generally atmospheric pressure with a controlled laminar air flow. The product being dried is sprayed into the drying chamber by an air distributor plate with a relatively rapid air flow through and immediately surrounding the product spray and with a surrounding air flow of lower velocity. The dried droplets or powder are removed by a powder collector including a drag system.

Abstract: A flowmeter for gases and liquids utilized a semi-conductor body disposed in the gas or liquid, respectively, one end of the semi-conductor body being heated by means of an electric resistance wire such that at temperature difference, and thereby a voltage difference is realized between the ends of the semi-conductor body. The reduction of the temperature difference, and thereby of the voltage difference, varying with the flow rate is utilized for determining the flow rate. This is effected with the assistance of an amplifier across whose input the semi-conductor body is coupled-in and on whose output a signal representing the flow rate appears.

Abstract: An improved lock washer is described for locking nuts or bolts into their fastened positions. A molded plastic washer has a series of integral dimples or lock projections extending radially outwardly and downwardly from one of the washer contact surfaces. These integral projections are turned circumferentially during the tightening of the nut or bolt and the circumferential positioning of the dimples resists an unscrewing movement of the nuts or bolts.

Abstract: A bag assembly is described for the filter bag collectors used in spray dryers or similar equipment which permits a quick change to fresh filler bags. The bag assembly includes a cage-like support for each of the individual filter bags which is inserted within the bags and which includes a bag attachment and sealing ring at its outer end. A pin-type connecting device employing a simple lifting and turning movement permits the bag assemblies to be quickly removed and remounted.

Abstract: An improved internal combustion engine and method of operation are disclosed. A method and a means are described for conserving mechanical energy in the engine cylinder during the combustion portion of the engine cycle by automatically adjusting the engine cylinder volume.

Abstract: An improved multicontact switch is disclosed which has a molded plastic body supporting a molded plastic rotor. Metallic contacts are resiliently mounted on the rotor in position to engage and bridge a second set of contacts provided in the form of a printed circuit formed on an inner surface of the switch cover. A versatile multicontact switch pattern is obtained by an appropriate layout of the printed circuit contacts in combination with a particular mounting arrangement of the contacts on the switch rotor.