Abstract: A system and method for testing an integrated circuit (IC) by using a boundary scan ring having registers coupled to a functional scan ring having registers within the integrated circuit in order to maximize test coverage, while minimizing test time. This is accomplished by shifting the boundary scan registers according to a clock signal while supplying data to the functional scan registers. The functional scan registers also supply data to the boundary scan registers. By appropriately interleaving input and output registers of the boundary scan ring, random data is supplied to the functional scan registers. This data may be scanned out of the boundary scan registers and compared with previously established test vectors in order to determine whether the device is performing as designed. Data may also be scanned out of the functional scan registers to augment the test coverage.

Abstract: A novel method and apparatus for eliminating shoot-through events during master-slave flip-flop scan operations to allow minimal test time of electronic circuit components is presented. Shoot-through scan problems introduced by loading mismatches on the TAP master and slave clock signal lines are solved by scanning an appropriate value into a programmable register, which increases the delay from master clock signal TCKM off to slave clock signal TCKS on and from slave clock signal TCKS off to master clock signal TCKM on.

Abstract: A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.