Abstract: A dynamic MOS one transistor cell memory having a plurality of divided bit lines and a corresponding plurality of flip-flop sense amplifiers. Each bit line being divided into two electrically balanced parts which run adjacent and parallel to each other, and extend from the input/output nodes of their corresponding flip-flop sense amplifier to a balanced data access bus. The balanced data access bus being connected, in turn, to balanced data access, or read/write, circuitry. By virtue of the connection of balanced bit, and bus lines, and balanced data access circuitry, to each flip-flop sense amplifier, the probability of reading errors due to circuit imbalances at the input/output nodes of the flip-flops is greatly lessened.