Abstract: A power loss reduction circuit and method for use in an output stage of a voltage converter is provided. The circuit has one transistor associated with a first output terminal of the output stage and ground. There is also a clamping circuit associated with the first output terminal. There is also a second transistor with a second conduction path associated with a second output terminal of the output stage and ground. The second transistor has a second control terminal controlled by a second control signal. Each of the first and second transistors has a lower voltage drop than a voltage drop for a Schottky diode. There is also a second clamping circuit associated with the second output terminal. There is also an energy storage device associated with the first and second clamping circuits to store energy from the first and second ringing signals.