Abstract: A method for testing a programmable, nonvolatile memory including a matrix of memory cells is provided. A plurality of memory cells are programmed. The programmed memory cells are addressed in succession to identify a lowest of threshold voltage levels. The addressing for each memory location includes applying a selection voltage that is lower than the lowest threshold voltage level corresponding to a memory location currently being addressed. The bits are read from the programmed memory cells for the memory location currently being addressed. The reading is repeated while progressively changing the selection voltage supplied to the word line corresponding to the memory location currently being addressed until it is detected that at least one of the bits of the memory location currently being addressed has switched from a first logic level corresponding to a reading of a programmed memory cell to a second logic level corresponding to a reading of a non-programmed memory cell.

Abstract: During critical plasma etching steps, the wafer's surface is illuminated with electromagnetic radiation in the visible and/or in the UV spectrum having an energy and power density sufficient to increase the reverse current through protective junctions on the wafer. These protective junctions provide electrical discharge paths for electrical charges picked up by exposed conductive parts of the wafer. The induced voltages are limited to values compatible with preserving the integrity of functional dielectric layers coupled to the exposed conductive parts and to the semiconductor substrate or to another conductive part.