Abstract: A reconfigurable signal processor receives continuously changing signal elements for analyzing signal patterns through a conversion process further defined by a coarse sample reference and a fine sample reference. Receiving the plurality of signal elements to produce raw data status representing specific signal elements, the coarse sample reference is used to sub-divide raw data patterns into a predetermined number of equal parts. The fine sample reference is used to define specific variations or gaps between the predetermined number of equal sub-divided parts for data patterns to trigger status updates in a bit-mapped memory array with a bit pattern mutually exclusive of logic one bit states. A decoder is used to convert sub-divided data patterns into a digital bit pattern of mutually exclusive logic one states which is stored in the memory away when triggered by specific variations or gaps between the predetermined number of equal sub-divided parts for signal data patterns.