Abstract: A method and apparatus are disclosed for controlling the operation of a multiphase motor, and particular to spinning the motor from an inactive state to an operable state. The method and apparatus include initially sensing an electrical characteristic of one or more phase windings, such as performing an inductive sense operation. Having sensed values of the electrical characteristic, a determination is made as to whether or not the motor's rotor is spinning. Upon a determination that the rotor is not spinning, a spin-up operation is performed to bring the spin of the rotor to operable spin speeds. On the other hand, upon a determination that the rotor is spinning, a resynchronization operation is performed to synchronize the application of drive signals for the phase windings of the motor to the dynamic position of the rotor.

Abstract: A communications system, a digital modem and method are provided for reducing non-linear distortion generated by a transmitter which adversely affects a receiver attempting to demodulate received data. More specifically, the digital modem includes a controller that controls a receiver and a transmitter. The receiver is operable to receive a plurality of receiver tones, and the transmitter is operable to generate a plurality of transmitter tones whose intermodulation products (transmitter non-linear distortion) conflict with the plurality of receiver tones. The transmitter is also operable to shift the plurality of transmitter tones by a predetermined distance to move the conflicting intermodulation products off the plurality of receiver tones.

Abstract: A memory chip which uses a multi-pin port as a JTAG port includes a JTAG controller, at least one internal block and a configuration unit which selectively configures four pins of the multi-pin port to communicate JTAG data to the JTAG controller or to communicate non-JTAG data to the at least one internal block. The configuration unit can be generally permanent or it can be modifiable. For example, the modifiable configuration unit can be a volatile memory (VM) configuration unit or a product term output of a programmable logic device (PLD).

Abstract: A pair of equivalent controlled impedance buffers are connected in a push-pull configuration to a transformer primary coil. A pair of equivalent pre-drivers are connected to the pair of buffers. Each pre-driver receives a driver input signal and outputs a buffer input signal and a proportional flyback compensation signal. Each buffer receives the buffer input signal generated from one of the pre-drivers for buffered output as a line driver signal to the primary coil which induces a flyback voltage effect in each buffer. Each buffer further receives the flyback compensation signal generated from the other one of the pre-drivers, with the buffer operating to cancel the flyback voltage effect induced in that buffer using the flyback compensation signal received from the other one of the pre-drivers. An adjustment circuit further outputs an adjustment signal for application to an adjustable current source.

Abstract: A dynamic random access memory (DRAM) circuit is provided that utilizes a testing system and method to determine the sensitivity of a sense amplifier. More specifically, the DRAM circuit, in determining the sensitivity of the sense amplifier, utilizes a testing system to independently control the magnitude of a voltage differential appearing between a pair of bit lines and sensed by the sense amplifier. The sensitivity of the sense amplifier is then able to be determined by monitoring an input/output signal in response to sensing the known voltage differential. The testing system controls the magnitude of the voltage differential appearing between the bit lines by enabling a first dummy cell to transfer a first reference charge onto a first bit line and by enabling a second dummy cell to transfer a second reference charge onto a second bit line.

Abstract: A clock generator or oscillator circuit for use in an integrated circuit for generating a clock signal includes a 555 timer circuit. The time constant circuit of the 555 timer includes a heater element for generating heat and a transducer for converting heat generated by the heater element into electrical energy. The clock signal is generated in response to the heating and cooling of the heater element.

Abstract: A bit line recovery circuit for random access memory. The circuit includes a pair of pull-up devices, each of which is connected to a bit line of a bit line pair. Pass gates are disposed between a sense amplifier and the bit lines. The pull-up devices are cross-coupled such that the gate node of the pull-up devices are connected to the sense amplifier on the opposed side of the pass gates in order to rapidly turn on the appropriate pull-up device following a memory cell read operation.

Abstract: A merged power device structure, of the emitter-switching type, in which the emitter of the bipolar power transistor has a minimum-width pattern which is aligned to the trenches of a trench control transistor. Thus the current density of the bipolar is maximized, since the emitter edge length per unit area is increased. The parasitic base resistance of the bipolar can also be reduced.

Abstract: An SRAM cell includes a pair of N channel transistors acting as inverting circuits, a pair of N channel transistors which perform the control function for the cell, and a pair of N channel thin film transistors in depletion mode with gate and source shorted to provide load devices for the N channel inverter transistors of the SRAM cell.