Abstract: In some embodiments, image spam is identified by comparing color histograms of suspected spam images with color histograms of reference (known) images. The histogram comparison includes comparing a first color content in a query image with a range of similar color contents in the reference image. For example, a pixel count for a given color in the query image may be compared to pixel counts for a range of similar colors in the reference image. A histogram distance between two images may be determined according to a computed pixel count difference between the given query histogram color and a selected color in the range of similar reference histogram colors.

Abstract: In some embodiments, processor-to-processor and/or broadcast proxies are designated in a microprocessor matrix comprising a plurality of mesh-interconnected matrix processors when default processor-to-processor or broadcast routing algorithms used by data switches within the matrix to route messages would not deliver the messages to all intended recipients. The broadcast proxies broadcast messages within individual non-overlapping broadcast domains of the matrix. P-to-P and broadcast proxies may be designated as part of a boot-time testing/initialization sequence. Improving system fault tolerance allows improving semiconductor processing yields, which may be of particular significance in relatively large integrated circuits including large numbers of relatively-complex matrix processors.

Abstract: In some embodiments, a video (e.g. MPEG-2, H.264) transcoder channel pool is used to transcode multiple independent videos (programs) per channel substantially concurrently. A syntactically-unified combined input video stream is assembled by interleaving segments of different input video streams. The combined stream may be a container stream or elementary stream. Each segment includes one or more groups of pictures (GOP). The combined stream includes the payload video data of the input streams in unmodified form, and modified header data characterizing the combined stream as a single video stream. The combined input stream is transcoded using a single transcoder channel/input port to generate a combined output video stream. Multiple independent output video streams are assembled by de-interleaving segments of the combined output video stream according to stored interleaving break identifiers.

Abstract: In some embodiments, a server system composites in real-time, in response to a user video search query, a standard-compliant (e.g. MPEG-4/H.264) SD or HD video stream encoding a rectangular (x-y) composite video preview panel array (grid) of video search results. Each panel/tile in the rectangular panel array displays a temporal section (e.g. the first 90 seconds, looped-back) of a video identified in response to the user query. Generating the composite video panel array in real-time is achieved by compositing the component video panels in the compressed domain, after each panel undergoes a compressed-domain pre-compositing preparation process that facilitates dynamic compositing of the panels into a single video stream. The pre-compositing preparation includes transcoding to a format having a down-scaled common resolution, common GOP structure, and one-slice-per-row slice structure.

Abstract: In some embodiments, a wearable physiologic monitor comprises a mixed analog and digital application-specific integrated circuit (ASIC) including signal conditioning circuitry, an A/D converter, a real-time clock, and digital control logic. The signal conditioning circuitry includes analog amplification circuitry, analog (continuous-time or switched capacitor) filtering circuitry before the A/D converter, and in some embodiments digital (DSP) filtering circuitry after the A/D converter. The monitor includes sensors such as electrocardiogram (ECG) electrodes, accelerometers, and a temperature sensor, some of which may be integrated on the ASIC. The digital control logic receives digital physiologic data sampled at different rates, assembles the data into physiologic data packets, time-stamps at least some of the packets, and periodically stores the packets in a digital memory. The monitor may include a disposable patch including the ASIC, and a reusable, removable digital memory such as flash memory card.

Abstract: In some embodiments, antivirus/malware behavior-based scanning (emulation) is accelerated by identifying known code sequences and executing pre-stored native-code routines (e.g. decompression, decryption, checksum routines) implementing the functionality of the known code sequences before returning to the emulation. During emulation, target machine code instructions are compared to a set of known signatures. If a known code sequence is identified, the emulator calls a native code routine and caches the current instruction address. If the emulator subsequently reaches a cached address, a native code routine may be called without scanning the data at the address for known signatures. Signature scanning may be performed selectively for instructions following code flow changes (e.g. after jump, call or interrupt instructions).

Abstract: According to some embodiments, an integrated circuit comprises a microprocessor matrix of mesh-interconnected matrix processors. Each processor comprises a data switch including a data switch link register and matrix routing logic. The data switch link register includes one or more matrix link-enable register fields specifying a link enable status (e.g. a message-independent, p-to-p, and/or broadcast link enable status) for each inter-processor matrix link of the processor. The matrix routing logic routes inter-processor messages according to the matrix link-enable register field(s). A particular link may be selected by a current matrix processor by selecting an ordered list of matrix links according to a relationship between ?H and ?V, and choosing the first enabled link in the selected list for routing.

Abstract: In some embodiments, an integrated circuit comprises a microprocessor matrix including a plurality of mesh-interconnected matrix processors, wherein each matrix processor comprises a data switch configured to direct inter-processor communications within the matrix, and a mapping unit configured to generate a data switch functionality map for a plurality of data switches in the microprocessor matrix. The data switch functionality map is generated by sending a first message through the matrix, and, setting a first functionality status designation for the first data switch in the data switch functionality map upon receiving a reply to the first message from a first data switch through the matrix.

Abstract: In some embodiments, a spam filtering method includes computing a pattern relevance for each of a set of message feature patterns, and using a neural network filter to classify incoming messages as spam or ham according to the pattern relevancies. Each message feature pattern is characterized by the simultaneous presence within a message of a specific set of message features (e.g., the presence of certain keywords within the message body, various message header heuristics, various message layout features, etc.). Each message feature may be spam- or ham-identifying, and may receive a tunable feature relevance weight from an external source (e.g. data file and/or human operator). The external feature relevance weights modulate the set of neuronal weights calculated through a training process of the neural network.

Abstract: In some embodiments, a system allowing a flexible upgrade of a computer system (e.g. server) to a high-speed network connection comprises base configuration motherboard or network card including a set of low-speed (e.g. 1 Gbps Ethernet) media access controllers (MACs) each connected to a low-speed physical controller (PHY), and a set of high-speed (e.g. 10 Gbps Ethernet) MACs. An expansion card including high-speed PHYs of choice can be connected by an end user to the base configuration motherboard or network card. A flow classifier classifies data sent/received over both high-speed and low-speed ports, and a single driver may control both high- and low-speed ports. One or both of the motherboard and/or expansion card are configured according to a detected type (e.g. physical layer standard, vendor) of expansion card connected to the motherboard and/or type of physical medium connected to the expansion card.

Abstract: In some embodiments, a layout-based electronic communication classification (e.g. spam filtering) method includes generating a layout vector characterizing a layout of a message, assigning the message to a selected cluster according to a hyperspace distance between the layout vector and a central vector of the selected cluster, and classifying the message (e.g. labeling as spam or non-spam) according to the selected cluster. The layout vector is a message representation characterizing a set of relative positions of metaword substructures of the message, as well as metaword substructure counts. Examples of metaword substructures include MIME parts and text lines. For example, a layout vector may have a first component having scalar axes defined by numerical layout feature counts (e.g. numbers of lines, blank lines, links, email addresses), and a second vector component including a line-structure list and a formatting part (e.g. MIME part) list.

Abstract: In some embodiments, a layout-based electronic communication classification (e.g. spam filtering) method includes generating a layout vector characterizing a layout of a message, assigning the message to a selected cluster according to a hyperspace distance between the layout vector and a central vector of the selected cluster, and classifying the message (e.g. labeling as spam or non-spam) according to the selected cluster. The layout vector is a message representation characterizing a set of relative positions of metaword substructures of the message, as well as metaword substructure counts. Examples of metaword substructures include MIME parts and text lines. For example, a layout vector may have a first component having scalar axes defined by numerical layout feature counts (e.g. numbers of lines, blank lines, links, email addresses), and a second vector component including a line-structure list and a formatting part (e.g. MIME part) list.

Abstract: In some embodiments, fully-automated spam identification is facilitated by accelerating a signature extraction process, allowing the use of a relatively large number of signatures finely tailored to individual spam waves, rather than a smaller number of highly-accurate signatures generated under human supervision. The signature extraction process is performed in a distributed manner. A message corpus is classified into a plurality of message clusters. Cluster-specific spam identification text patterns are extracted selectively from members of each cluster, and the text patterns are combined into cluster-specific spam identification signatures. A cluster may represent an individual spam wave. Genetic algorithms are used to optimize the set of spam identification signatures by selecting the highest-performing combinations of cluster-specific spam identification text patterns.

Abstract: In some embodiments, each matrix processor in a matrix of mesh-interconnected matrix processors includes an instruction processing pipeline, and a hardware data switch capable of streaming data to/from one or more inter-processor matrix links and/or a matrix processor local memory links in response to execution of a data streaming instruction by the instruction processing pipeline. The data switch can transfer each data stream, which includes multiple words, at wire speed, one word per cycle. After initiating a data stream, the processing pipeline can execute other instructions, including streaming instructions, while a stream transfer is in progress. Different data streaming instructions may be used to transfer data streams from local memory to one or more inter-processor links, from an inter-processor link to local memory, from an inter-processor link to one or more inter-processor links, and from an inter-processor link to one or more inter-processor links and synchronously to local memory.

Abstract: In some embodiments, a layout-based electronic communication classification (e.g. spam filtering) method includes generating a layout vector characterizing a layout of a message, assigning the message to a selected cluster according to a hyperspace distance between the layout vector and a central vector of the selected cluster, and classifying the message (e.g. labeling as spam or non-spam) according to the selected cluster. The layout vector is a message representation characterizing a set of relative positions of metaword substructures of the message, as well as metaword substructure counts. Examples of metaword substructures include MIME parts and text lines. For example, a layout vector may have a first component having scalar axes defined by numerical layout feature counts (e.g. numbers of lines, blank lines, links, email addresses), and a second vector component including a line-structure list and a formatting part (e.g. MIME part) list.

Abstract: According to some embodiments, CD/DVDs are transported to/from a horizontal tray of a disk-processing unit (e.g. a disk drive) by applying a vertical lifting force to each disk at an off-center disk engagement location to incline the disk toward the tray, maintaining the disk in an inclined position toward the processing unit during a vertical travel to/from the tray; and gliding the disk into the tray from the inclined position to a final horizontal position by vertically delivering the disk into the tray. In some embodiments, a CD/DVD transfer apparatus comprises a pickup head for picking up and releasing disks, a horizontal-motion arm driving a horizontal motion of the pickup head, and a flexible vertical connection coupling the pickup head to the horizontal-motion arm. The flexible vertical connection is formed by a section of a flexible wire, thread, ribbon or tape coiled on a reel situated above the pickup head.

Abstract: In some embodiments, control and data messages are transmitted non-contentiously over corresponding control and data channels of inter-processor links in a matrix of mesh-interconnected matrix processors. A data stream instruction executed by a user thread of an instruction processing pipeline of a matrix processor may initiate a data stream transfer by a hardware data switch of the matrix processor over multiple consecutive cycles over a data channel. While the data stream is being transferred, the corresponding control channel may transfer control messages non-contentiously with respect to the data stream. The control messages may be messages received from other matrix processors and/or control messages initiated by a kernel thread of the current matrix processor.

Abstract: In some embodiments, a hardware linked-list manager includes a wildcard search controller for generating corresponding queue-specific read requests from wildcard read requests. The linked-list manager may be part of an on-chip interagent switch for allowing a plurality of agents to communicate with each other. The interagent switch may include a crossbar switch and a plurality of hardware linked-list managers integrated on the chip, connected to a random access memory, and connected to the crossbar switch such that the crossbar switch is capable of connecting each of the linked-list managers to each of the agents. Each linked-list manager sends agent-generated data to the memory for storage in the memory as a linked-list element, and retrieves linked-list elements from memory in response to agent read requests. A shared free-memory linked-list manager may maintain a linked list of free memory locations, and provide free memory address locations to a linked list manager upon request.

Abstract: According to some embodiments, a multithreaded microcontroller includes a thread control unit comprising thread control hardware (logic) configured to perform a number of multithreading system calls essentially in real time, e.g. in one or a few clock cycles. System calls can include mutex lock, wait condition, and signal instructions. The thread controller includes a number of thread state, mutex, and condition variable registers used for executing the multithreading system calls. Threads can transition between several states including free, run, ready and wait. The wait state includes interrupt, condition, mutex, I-cache, and memory substates. A thread state transition controller controls thread states, while a thread instructions execution unit executes multithreading system calls and manages thread priorities to avoid priority inversion. A thread scheduler schedules threads according to their priorities.