Abstract: A personal audio playback device having gain control responsive to environmental sounds provides for improved enjoyment of program material played back through headphones, while further providing features for personal safety and communications with others. A microphone is incorporated on the surface of the playback device, which includes an audio output connection for headphones and internal storage for audio program material. The entire device may be incorporated within the headphones, or the headphones may connect through a connector on the housing of the device. The gain, type or position of the program material is controlled in conformity with a detected characteristic of ambient sounds received by the microphone, which may be the amplitude of the signals in one or more frequency bands, or a particular type of sound, such as speech or vehicular sounds. Multiple modes are selectable for processing the audio, selecting program material type and/or re-positioning the program material.

Abstract: A charge-pump biased battery protection circuit provides improved efficiency, reduced power dissipation, and reduced complexity in battery powered circuits. A charge pump is utilized to bias the gate of a single pass transistor such that the voltage between the pass transistor gate and the drain/source terminals of the pass transistor have a magnitude greater than the battery voltage, reducing the voltage drop across the pass transistor. The charge pump may be controlled in conformity with a sensed current through the pass transistor, so that at times of lower current loads, power is conserved. The bulk (body) of the pass transistor can be controlled using a resistor coupling a battery terminal to the bulk and a single switch coupling the bulk to a charger/load connection terminal, permitting a single pass transistor to be used for charging and discharging.

Abstract: A thermal overload protection circuit and method for protecting switching power amplifier circuits provides protection against latch-up and other failures due to energy returned from an inductive load when the amplifier output is disabled in response to a thermal overload condition. Upon detection of a thermal overload condition, rather than immediately disabling the switching power output stage, the switching power output stage is driven toward a fifty-percent duty cycle of operation for a predetermined time period so that energy stored in inductance of the load is reduced, preventing back-currents that would otherwise may cause latch-up within the integrated circuit when the switching power output stage is disabled. After the time period has elapsed, the switching power output stage is disabled. Alternatively, the current through the inductive load is measured and the switching power stage is disabled after the magnitude of the current has fallen below a threshold.

Abstract: A method and apparatus for generating a clock signal according to an ideal frequency ratio provides flexible and reduced frequency error clock generation. A ratio control number is specified or is determined from a phase-frequency comparison of the clock signal to a timing reference. A correction factor is specified as a numerator and denominator and an error is accumulated according to the numerator and denominator of the correction factor. The ratio control number is adjusted according to the accumulated error so that an ideal ratio is maintained between the frequency of the clock signal and the frequency of the timing reference. If the ratio is determined from a phase-frequency correction, then the phase-frequency error is adjusted so that a loop filter output is corrected on average. Otherwise, the ratio control number is adjusted directly.

Abstract: A direct digital synthesis (DDS) hybrid phase-lock loop for low-jitter synchronization provides a mechanism for generating a low-jitter clock from a timing reference that has a high jitter level. A DDS circuit provides a clock output and has an input for receiving a rational number. The rational number represents a ratio between the frequency of the clock output and the frequency of another stable clock provided to the circuit. In one implementation, a phase output of the DDS circuit is compared to a phase determined from an incoming timing reference and in another implementation, the low-jitter clock output is utilized to generate a phase number via a counter that is clocked by the clock output and captured by the timing reference.

Abstract: An over-current protection circuit protection circuit and method for protecting switching power amplifier circuits provides protection against latch-up and other failures due to energy returned from an inductive load when one or more transistors in the amplifier output are disabled in response to an over-current condition. Upon detection of an over-current condition, the transistor corresponding to the over-current conduction direction is disabled. At the same time, the transistor corresponding to the conduction direction opposite the over-current direction is enabled for a predetermined time period, or until the magnitude of the load current has dropped, so that energy stored in inductance of the load is reduced, preventing back-currents that would otherwise cause latch-up and consequent destruction of the output stage when the switching power output stage is disabled. After the predetermined time period has elapsed or the load current has dropped below a threshold, the entire output stage is disabled.

Abstract: A digital-to-analog converter (DAC) having filter sections with differing polarity provides a low-noise, low area bipolar output solution in delta-sigma modulator based DACs. A shift register receives an input bit-stream and provides a series of tap outputs that are used to control application of a number of current sources to output summing nodes. The current sources are divided into mutually-exclusive sets of positive polarity and negative polarity current sources, which are not necessarily contiguous. In one embodiment, half of one of the sets of current sources precedes the other set of current sources, and the other half of the divided set of current sources provides the final set of output taps. The number of current sources in each set may be equal, so that the midpoint of the output corresponds to zero current.

Abstract: A method and apparatus for reducing switching noise in a system-on-chip (SoC) integrated circuit including an analog to digital converter (ADC) provides for reduced noise in the ADC conversions. Sampling circuits of the ADC are operated by sampling clock signals and digital circuits and other noise-generating circuits such as power converters, are operated by digital circuit clock signals. Both sets of clock signals are derived from the same master clock by a clock generator circuit, but an offset is applied in the clock generator circuit to move the edges of the digital circuit clock signals away from critical sampling intervals corresponding to edges of the sampling clocks. In one embodiment, the offset is applied by a processor core that forms part of the digital circuits by setting a value in the clock generator, which the clock generator then loads into the divider after halting the clock to the digital circuits.

Abstract: A power-optimized analog-to-digital converter (ADC) input circuit provides for optimized power consumption versus performance. The first amplifier stage of the ADC is provided by a plurality of amplifiers that are selectably enabled to provide a particular bandwidth and noise performance level. The selection of the combination of enabled amplifiers may be made in conformity with the sample rate of the converter and the amplifiers may have evenly-weighted bias currents, or unevenly weighed bias currents and may be optimized for their particular use in combinations for bandwidth and 1/f noise corner performance. The outputs of the amplifiers are combined in a combiner circuit, which may be a discrete-time chopping amplifier that receives charges from a plurality of capacitors that sample each enabled amplifier output.

Abstract: A video quality adaptive variable-rate buffering method and system for stabilizing a sampled video signal reduces the buffer size required to compensate for line-to-line variations in an unstable video source. A video signal is sampled at a predetermined rate and decimated by a selectable decimation factor prior to buffering. By selecting different decimation factors, the effective length of the buffer is changed from short duration for stable input signals and to longer duration for unstable input signals. A video signal quality detector is employed to provide a selection input that adjusts the decimation factor and also the loop bandwidth of a clock generator that provides the output clock for the buffer, which is generated from the input signal via a phase-lock loop (PLL). The operation of the system automatically varies from highly responsive for stable video input signals to less responsive for unstable video input signals, providing improved stability in the video output.

Abstract: An analog-to-digital converter (ADC) having a reduced number of quantizer output levels provides for reduced complexity and power consumption along with improved linearity. The analog-to-digital converter includes a loop filter, a quantizer for quantizing the output of the loop filter and a digital integrator for integrating the output of the quantizer. A difference circuit is included in the converter that produces a signal proportional to the difference between the present value and a previous value of the digital integrator output and provides feedback to the loop filter. The number of levels of the quantizer output is thereby reduced with respect to the modulator output, since the quantizer is operating on a feedback signal that represents changes in the output of the converter modulator rather than the modulator output itself.

Abstract: An analog-to-digital converter (ADC) having integrator dither injection and quantizer output compensation reduces the probability of unchanging code sequences that occur when the input signal and feedback signal are equal and thus no quantizer output change occurs. In particular, in modulators that are periodically reset, the dither reduces the probability of a stuck code sequence at startup. The effect of the dither is removed from the output of the ADC, either by subtracting an offset value from the result of filtering the quantizer output, or directly from the quantizer output itself.

Abstract: A system-on-chip (SoC) integrated circuit including an interleaved delta-sigma analog to digital converter (ADC) provides for reduced noise in the ADC conversions. The ADC is operated intermittently and the balance of the digital circuits forming the system are halted while the conversions take place. The halted portion of the system may include an output low-pass filter of the ADC. The system may include a processor core or other logic having a clock frequency unrelated to the ADC modulator clock frequency that is not otherwise clock-managed to reduce noise induced in the converter output by the operation of the core or other logic.

Abstract: A feedback topology delta-sigma modulator having an AC-coupled feedback path reduces signal level in the loop filter, easing linearity requirements and reduces capacitor size requirements for the filter integration stages. The delta-sigma modulator includes a loop filter having multiple integrator stages, a quantizer, and a feedback network providing at least two feedback paths to corresponding integrators in the loop filter. In one aspect, only one of the feedback paths from the quantizer output is DC coupled, and at least one other of the feedback paths is DC-coupled, which reduces the signal levels in the loop filter integrators. In another aspect, at least one of the feedback paths from the quantizer is AC coupled, providing a similar result. The AC feedback path may be provided through a series-connected resistor and capacitor. The DC feedback path may be provided through a resistor, a switched-capacitor network, or may be a quantizer-controlled current source.

Abstract: A magnetic field feedback delta-sigma modulator sensor circuit, provides accurate magnetic field measurements without requiring complex additional calibration circuitry. The output of the semiconductor magnetic field sensor, which may be a Hall effect sensor, is coupled to the input of the delta-sigma modulator loop filter. The output of the quantizer of the delta-sigma modulator is magnetically coupled to the magnetic field sensor, producing a field that causes the output of the sensor to be canceled for frequencies in the band of the modulator loop filter. The output of the quantizer is provided to a current output digital-to-analog converter, which feeds a current loop that is inductively coupled to the sensor body. A chopper amplifier can be provided between the output of the sensor and the modulator loop filter input to reduce 1/f noise and bias current and output terminals can be rotated to further reduce 1/f noise and offset.

Abstract: An electrically operable valve assembly having an integral pressure regulator provides ease of installation and compact packaging for a water supply control system. The valve assembly is particularly useful for systems that control household water supplies to prevent flooding, but is also useful in other applications such as agricultural and industrial systems where water pressure determined water flow volume must be predicted accurately. The valve may also incorporate a flow meter having a positive flow characteristic permitting determination of very low flow rate flow and the valve may incorporate a manual control. All of the controls and features are integrable within a compact package that occupies essentially the same volume and piping space as a conventional electrically operable valve.

Abstract: A flow meter and electrically operable valve assembly having integral flow meters provide detection of very low water flows, along with ease of installation and compact packaging for a water supply control system. The flow detection is particularly useful for systems that control household water supplies to prevent flooding, but is also useful in other applications such as agricultural and industrial systems where low water flow rates must be determined. All of the controls and features are integrable within a compact package that occupies essentially the same volume and piping space as a conventional electrically operable valve.

Abstract: AC/DC cascaded power converters having high DC conversion ratio and improved AC line harmonics provide low input harmonic currents, high power factor and efficient operation for low voltage DC outputs when coupled directly to a source of unfiltered rectified AC voltage. The power converter incorporates an intermediate storage element that provides most or all of the energy storage capacitance within the power converter and a blocking device that enables continuous energy transfer from AC line to output to achieve unity power factor and regulated output while maintaining low AC input current ripple.

Abstract: An apparatus and method for programmable control of laser diode modulation and operating point provides control for laser diodes having widely varying characteristics, such as laser diodes from a variety of manufacturers. Operating a wide variety of lasers is useful for implementation of a device independent integrated circuit for control of a laser diode. Laser diode maximum AC drive levels, AC input circuit response and DC operating point are programmed via a programmable storage coupled via control circuits to a drive amplifier and a bias circuit. The laser diode modulation control may be combined with laser diode bias control in a single integrated circuit, providing a single-chip solution for laser diode transceiver module manufacturers. The programmable storage may be one-time programmable for factory customization of laser diode transceiver module diodes, or may be an electrically alterable storage.

Abstract: A method and system for power node current waveform modeling provides improved accuracy for logic gate and functional block power node current models in computer-based verification and design tools. An output voltage waveform is generated, with each point a linear function of a set of input values corresponding to times at which the output voltage reaches predetermined fractions of the supply voltage. A set of coefficients is used for each point, as each output voltage has a different linear dependency on the input values. The output voltage waveform model is differentiated and multiplied by an effective load capacitance to determine an output current waveform. The method and system retain compatibility with existing software by using input values already present in the digital simulation models (e.g., delay times) that yield a subset of output voltage points. The coefficients of the model are predetermined for a circuit from principle components analysis.