Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

Abstract: A system resource enable apparatus for enabling operations on a system resource including a register representing current and future operations on the resource, a pattern generator that applies a pattern corresponding to a requested resource operation to each of a plurality of requests for resource operations in a queue, compare logic that determines for each of the plurality of requests if the request will conflict with other resource operations by comparing the pattern applied to the request with the register, priority grant logic that grants priority to a request in the queue if no conflict is determined and to update the register according to the pattern applied to the request, and resource enable logic that enables operations on the resource according to the register.

Abstract: A system resource enable apparatus for enabling operations on a system resource including a register representing current and future operations on the resource, a pattern generator that applies a pattern corresponding to a requested resource operation to each of a plurality of requests for resource operations in a queue, compare logic that determines for each of the plurality of requests if the request will conflict with other resource operations by comparing the pattern applied to the request with the register, priority grant logic that grants priority to a request in the queue if no conflict is determined and to update the register according to the pattern applied to the request, and resource enable logic that enables operations on the resource according to the register.

Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

Abstract: A system resource enable apparatus for enabling operations on a system resource including a register representing current and future operations on the resource, a pattern generator that applies a pattern corresponding to a requested resource operation to each of a plurality of requests for resource operations in a queue, compare logic that determines for each of the plurality of requests if the request will conflict with other resource operations by comparing the pattern applied to the request with the register, priority grant logic that grants priority to a request in the queue if no conflict is determined and to update the register according to the pattern applied to the request, and resource enable logic that enables operations on the resource according to the register.

Abstract: A system resource enable apparatus for enabling operations on a system resource including a register representing current and future operations on the resource, a pattern generator that applies a pattern corresponding to a requested resource operation to each of a plurality of requests for resource operations in a queue, compare logic that determines for each of the plurality of requests if the request will conflict with other resource operations by comparing the pattern applied to the request with the register, priority grant logic that grants priority to a request in the queue if no conflict is determined and to update the register according to the pattern applied to the request, and resource enable logic that enables operations on the resource according to the register.

Abstract: A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper.Our I/O zipper concept can be used to implement the concept that the port into a node could be driven by the port out of a node or by data coming from the system bus. Conversely, data being put out of a node would be available to both the input to another node and to the system bus. Outputting data to both the system bus and another node is not done simultaneously but in different cycles. The zipper passes data into and out of a network of interconnected nodes is used in a system of interconnecting nodes in a mesh, rings of wrapped tori. such that there is no edge to the network, the zipper mechanism logically breaks the the rings along a dimension orthogonal to the rings such that an edge to the network is established. The coupling dynamically toggles the network between a network without an edge and a network with an edge.

Abstract: A parallel computer system providing multi-ported intelligent memory is formed of a plurality of nodes or cells interconnected to provide a shared memory with processors of the network and their memory providing the network routing and shared memory. Each of the nodes provides a functional unit with a processor, shared memory, and communication interface. K zipper ports in addition provide a switching function to interconnect the distributed memory and processors providing the shared memory. The resulting multi-ported shared intelligent memory switch can be used to connect (switch) a variety of computer system elements (CSEs) including computers and direct access storage devices (DASDs). The multi-ported intelligent memory shared memory organized into a collection of cells or nodes and is called the hedgehog. Each node comprises a finite computer memory, a processing unit, and communication interface and at least K of the nodes of the device have a zipper port.

Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

Abstract: A resource arbitration system is provided implementing a modified round robin priority selection logic including resource checking and lockout avoidance that updates the round robin priority token only when (1) the process request is granted and (2) there are no prior processes with resource conflicts. The resource arbitration system thereby allows each process request to get into the queue with high priority once the requested resource is freed.

Abstract: A Parallel RISC computer system is provided by a multi-mode dynamic multi-mode parallel processor array with one embodiment illustrating a tightly coupled VLSI embodiment with an architecture which can be extended to more widely placed processing elements through the interconnection network which couples multiple processors capable of MIMD mode processing to one another with broadcast of instructions to selected groups of units controlled by a controlling processor. The coupling of the processing elements logic enables dynamic mode assignment and dynamic mode switching, allowing processors operating in a SIMD mode to make maximum memory and cycle time usage. On and instruction by instruction level basis, modes can be switched from SIMD to MIMD, and even into SISD mode on the controlling processor for inherently sequential computation allowing a programmer or complier to build a program for the computer system which uses the optimal kind of parallelism (SISD, SIMD, MIMD).