Patents Represented by Attorney Ann Livington

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  • MOSFET cell array
    Patent number: 5365082
    Abstract: A CMOS memory cell array, and a process for making it, that avoids problems caused by LOCOS isolation of cells. Moats are formed by etching away columns of a thick field oxide layer. The moats have two-tiered sidewalls, such that an upper tier is sloped, and a lower tier is more vertical. This approach provides the advantages of sloped sidewalls, but avoids filament problems. After the moats are formed, subsequent fabrication steps may be in accordance with conventional fabrication techniques for CMOS arrays.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: November 15, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Manzur Gill, Pradeep L. Shah, Dave J. McElroy