Abstract: A mapping language, insertable into a DTD, allows automatic mapping from data sources into XML. A mapping results from the establishment of a correspondence between entities in a data source on the one hand and lists and scalars on the other hand. The language maps the lists and scalars to XML elements and attributes. The mapping language includes two constructs: the binding specification and the value specification. The value specification associates with a value or choice declaration. The binding specification includes at least one variable/expression pair. The constructs are insertable into a DTD to create an annotated DTD.

Abstract: In order to achieve interoperability between diverse types of computer systems for the purpose of e-commerce, a system and method are provided for retrieving data from multiple relational databases into an XEDI document. First, a DTDSA is used to create an intermediate format for the data. Then, an annotated interoperable (universal) DTD is used to create the XEDI document. For depositing data from an XEDI document into multiple relational databases, a reverse process is used. The universal DTD is used to create the intermediate format. Then the DTDSA is used to create the relational database format. The deposit process requires analysis of join unions of data sought to be deposited, and also a static reversibility check for the DTDSA. A GUI interface is provided for generating annotations.

Abstract: A multiport register file includes a first file unit having registers of a first width and a second file unite having registers of a second width. The second width being less than the first width. The first file unit accommodates data destined to be operands for functional units of a VLIW processor, or result data from those functional units. The second file unit accommodates guard bits for conditioning operation of those functional units.

Abstract: In a CELP coder, a comparison between a target signal and a plurality of synthetic signals is made. A synthetic signal is derived by filtering a plurality of excitation sequences by a synthesis filter having parameters derived from the target signal. The excitation signal, which results in a minimum error between the target signal and the synthetic signal, is selected. The search for the best excitation signal requires a substantial computational complexity. To reduce the complexity, a preselection of a small number of excitation sequences is made by selecting a small number of excitation sequences resembling the most backward filtered target signal. With this small number of excitation sequences a full complexity search is made. Due to the reduced number of excitation sequences involved in the final selection the required computational complexity is reduced.

Abstract: In order to enhance the dissipation of heat, a metal structure is provided between an anode target layer and a support for the anode target layer in an X-ray tube. In the case of a target transmission tube, notably the dissipation of heat to the window wall is enhanced, whereas in the case of an anode target layer provided on a suitably thermally conductive anode body, the dissipation of heat to said body is enhanced.

Abstract: A method and system for effectively and efficiently constructing a development environment for graphical user interfaces for an electronic consumer product. The basic aim of the invention tool is to automatically generate an interface in the authoring environment for customer specific target control components. This is done so by automatically creating a host platform control component (in the format of an OCX) from an existing target platform control component (in the format of a C header file). After running the invention once for every control component, a designer can then write on the host, for instance Visual Basic application code that performs calls to properties and methods of these generated control components.

Abstract: A user interface for a screen oriented electronic device includes a rotating menu of options. Options are highlighted and therefore selectable as they rotate past a fixed position on the screen. A remote is shown for use with the menu.

Abstract: An object detecting apparatus uses a radar system 24 which employes a directional antenna 6. A transmission parameter of the system 24 is calibrated for each transmission direction such that, at a boundary 22 of a detection area 20, there is a maximum signal intensity and a minimum sensitivity. The calibration is effected using reflectors of known reflective response which are positioned around the boundary 22 during calibration.

Abstract: A method for specifying a system comprising a plurality of interconnected functional modules each representing a respective abstract-state based machine, and a system so specified. A system is specified to include various interconnected functional modules at respective hierarchical levels. Each module represents an abstract state-based-machine. Each non-top level first module connects to a single second module at a next higher level by a transformer link from the second module for enabling a relevant change-of-state of the first module, by an observer link for a state enquiry signal from the second module, and by an event link for a solicited event signal to the second module. The first module retrosignals an internal autonomously executed step. Each non-bottom module enables one or more lower level modules to function as such first module. A top module can exchange signals with an environment.

Abstract: Cache layout is simplified by swizzling the bits of instruction words. Then the words are read out of cache by using a shuffled bit stream which simplifies cache layout. The object is further met using a cache structure which includes a device for storing a shuffled instruction stream; and a device for multiplexing bits from the storage means onto the bus so that the bits are deshuffled. The multiplexing means includes a multiplicity of lines leading from the storage device to the bus. The read lines do not cross each other.

Abstract: Cost/performance of VLIW architecture is improved by reducing the number of slots in the instruction issue register.

Abstract: The invention relates to an input system for at least location and/or street names, including an input device, a data source arrangement which contains at least one list of locations and/or streets, and a control device which is arranged to search location or street names, entered via the input device, in a list of locations or streets in the data source arrangement. In order to simplify the input of location and/or street names, the data source arrangement contains not only a first list of locations and/or streets with alphabetically sorted location and/or street names, but also a second list of locations and/or streets with location and/or street names sorted on the basis of a frequency criterion. A speech input system of the input device conducts input in the form of speech to the control device. The control device is arranged to perform a sequential search for a location or street name, entered in the form of speech, as from the beginning of the second list of locations and/or streets.

Abstract: A data processor, includes a central processing unit, an interrupt handler for selectingly signalling a single interrupt vector to the central processing unit, and multiple interrupt sources that are daisy-chained to the interrupt handler, for therewith exchanging interrupt request signals and interrupt acknowledge signals. A Bus (or buses) interconnects all above subsystems. The interrupt handler communicates a read vector command to all interrupt sources in parallel and thereupon allows transmitting an actual interrupt address vector on the bus.

Abstract: A method for configuring a wireless network comprised of a control node and a multiplicity of individual nodes includes the steps of logically organizing the network into a plurality of bands Bi, wherein each of the bands Bi includes a plurality of the individual nodes and is located a number i of hops away from the control node, where i=0 through N, and N.gtoreq.1, and then assigning a logical address to each of the individual nodes, and storing the assigned logical addresses in the respective individual nodes. The assigned logical address for each individual node includes a first address portion which indicates the band Bi in which that individual node is located, and a second address portion that identifies that node relative to all other individual nodes located in the same band. The network is preferably a packet-hopping wireless network in which data is communicated by transferring data packets from node-to-node over a common RF channel.

Abstract: Cost/performance of VLIW architecture is improved by reducing the number of slots in the instruction issue register.

Abstract: A calibration method and device are described, notably for a component-placement machine for placing components (30) on a carrier (3), which machine comprises carrier-positioning means (50) and component-positioning means (26, 27, 11; 40). The positions of components placed on a calibration carrier (60, 65) during a calibration procedure is detected by means of a calibration carrier detection device (50) which is present in the machine itself. For obtaining a satisfactory contrast between the components (30) and the calibration carrier surface, the latter may be provided with a reflecting and adhesive foil (65, 66). In a machine provided with a production carrier detection device, this device may be used as a calibration carrier detection device.FIG. 3.

Abstract: A FIFO unit for buffering serial communications includes a register and a unit for maintaining a single pointer. The single pointer functions as an IN pointer during writes and an OUT pointer during reads. The same circuitry maintains the pointer for both reads and writes to the FIFO. This circuitry preferably includes a single counter. If an error occurs during reading, the single pointer can be reinitialized and reading restarted, without loss of data. The register is not erased until reading is complete.

Abstract: A computer system enables a user to browse a hierarchically classified database by interactively displaying a relevant portion of the classification scheme of the database as category names and sub-category names. After a user selects a displayed category (or sub-category), the system automatically modifies the displayed relevant portion of the classification scheme in a way that is dependent on the particular selected category. The modified portion of the classification scheme that is displayed includes not only the name of the user selected category and some of the names of sub-categories thereof, but also the names of some non-selected categories that are on the same hierarchy level as the selected category and are relevant to the selected category, as well as some of the names of sub-categories of these non-selected categories, thereby helping the user to find the name of a category or sub-category of interest without overwhelming the user with too many displayed names of categories and sub-categories.

Abstract: The invention provides an apparatus for measuring a property of a sample (using, e.g., ISTS) that includes: 1) an excitation laser that generates an excitation laser beam; 2) an optical system aligned along an optical axis that separates the excitation laser beam into at least three sub-beams; 3) an imaging system aligned along the optical axis that collects the sub-beams and focuses them onto the sample to form an optical interference pattern that generates a time-dependent response in the sample; 4) a probe laser that generates a probe laser beam that diffracts off the time-dependent response to form a signal beam; 5) a detector that detects the signal beam and in response generates a radiation-induced electronic response; and 6) a processor that processes the radiation-induced electronic response to determine the property of the sample.

Abstract: A microcontroller with a page zero mode where a memory address space is restricted to one page of a multiple page address space to produce improved performance. Address mapping logic and memory segment selection logic limits addresses to the least significant 16 bits of a possible 24 bit address. Different or alternate microcode program controlled instruction sequences with eliminated high order address clock cycles are used in the page zero mode.