Abstract: Timing signal generation and distribution are combined in operation of a signal path exhibiting endless electromagnetic continuity affording signal phase inversion and having associated regenerative active means. Two-or more-phases of substantially square-wave bipolar signals arise directly in travelling wave transmission-line embodiments compatible with semiconductor fabrication including CMOS. Coordination by attainable frequency synchronism with phase coherence for several such oscillating signal paths has intra-IC inter-IC and printed circuit board impact.

Abstract: A method and aparatus for operating logic circuitry with recycled energy. Logic circuitry is used which has a node for storing energy and a return node that is connected to energy storage circuitry. The logic circuitry operates, using energy stored on the node, to determine a logic output based on a logic input during a first phase. The energy storage circuitry capture a portion of the stored energy during the operation of the logic circuitry and transfers a portion of the captured energy back to the node during a second phase. The energy storage circuitry oscillates with a determinable period and is tunable so that its oscillations can be synchronized to a clock.

Abstract: A system is described capable of excising individual cells in an N-dimensional array and healing the array connectivity without manual intervention. Thus cells that fail can be deleted and the array remain viable, although possibly requiring re-synchronization procedures to be performed. The system allows either replacement of bad cells or bypassing of bad cells, with appropriate cost and operational differences. Both level sensitive and edge sensitive excision mechanisms are described and the consequences of each discussed. The invention applies to processor arrays with one cell per physical chip or many cells per chip, and handles uni-directional or bi-directional data flows, and is generally both interface independent and technology independent.

Abstract: Dynamic low-power logic using recycled energy is disclosed. Logic circuits have a discharge path, a precharge path and a control circuit. The precharge path is a PMOS transistor coupled between the clock line and the output node of the circuit and configured to charge the output node to the logic high voltage of the clock line during a precharge phase. During an evaluation phase, the discharge path computes the desired logic function at the output node. A control circuit is connected between the output node and the clock line and to the gate of the precharge path transistor. The control circuit provides the proper gate drive, regardless of the voltage on the output node or the inputs to the discharge path, to guarantee that the precharge transistor fully charges the output node to the logic high voltage of the clock line, which provides recycled energy for operating the circuit.

Abstract: A voltage regulator for providing a bidirectional current and a regulated voltage to a load. The voltage regulator regulates the output voltage at one half the level of the input voltage using a voltage doubler circuit in reverse. The regulator provides current to the load when the output voltage drops and receives current from the load when the output voltage rises. The voltage regulator is particularly suited to supplying a termination voltage to multiple line drivers in a DDR DRAM system, where the line drives require an active termination voltage to reduce power. Additionally, a pair of linear regulators, one for clamping the output voltage at a predetermined low voltage level and for supplying additional current demanded by the load, and the other for clamping the output voltage at a predetermined high voltage level and for receiving additional current supplied by the load, is included.

Abstract: A logic circuit for evaluating a logic function while a signal on a clock input is a logic high. The logic circuit pre-discharges an output node to the logic low of the signal on the clock input and then charges the output node to logic high from the clock input when the logic function of the input is such as to require the output node to change state. The pre-discharge path is an n-channel transistor that is conductive only when the signal on the clock input is low. Also disclosed is a logic circuit that evaluates a logic function while a signal on the clock input is a logic high and while the signal on the clock input is a logic low, thereby permitting logic evaluations on both phases of the signal on the clock input.

Abstract: A multi-dimensionally layered encoding and decoding system having reduced the bandwidth requirements for a channel that carries an image stream encoded by the system. A source image stream is partitioned multi-dimensionally into a lower resolution layer and higher resolution layer image stream. The lower resolution image stream is encoded and decoded in accordance with certain accepted standards such as MPEG-2, MPEG-4 and JPEG. In the encoding of the lower layer image stream, a number of indicator signals are derived that indicate where a compression loss and resolution loss occurs. Additionally, the lower layer image stream is non-linearly processed to create an improved image stream and non-linear indicator for use in the upper-layer encoder. The upper-layer encoder uses the non-linear processed image stream and a decoded, reconstructed upper-layer encoded stream to derive the motion vectors and prediction frames in a motion compensation process.

Abstract: A system for extending standard processors using either undefined op-codes or sparse address spaces to maintain the use of legacy processor tools and reduce the complexity of the design process. The disclosure describes a method and apparatus for adding circuitry to processing units that allows partitioning of the design into a fixed processing unit derivative and a configurable subsystem. The legacy processor unit language tools work with the fixed processing unit derivative while the logic design tools work well with the configurable subsystem. In one embodiment, the configurable subsystem is implemented with easily available programmable Logic Devices (PLD's and FPGA's).

Abstract: A method and apparatus for operating logic circuitry with recycled energy. Logic circuitry is used which has a node for storing energy and a return node that is connected to energy storage circuitry. The logic circuitry operates, using energy stored on the node, to determine a logic output based on a logic input during a first phase. The energy storage circuitry capture a portion of the stored energy during the operation of the logic circuitry and transfers a portion of the captured energy back to the node during a second phase. In one embodiment, the logic circuitry and the energy storage circuitry form a resonant circuit and the logic circuitry operates synchronously to a clock. In another embodiment, the energy storage circuitry includes a resonant circuit configured to oscillate with a determinable period. The resonant circuit is tunable so that its oscillations can be synchronized to a clock.

Abstract: A method and apparatus for operating logic circuitry with recycled energy. An energy storage device such as an inductor collects energy that used to operate logic circuitry during a first phase of a clock cycle and returns the collected energy back to the circuit during a second phase of the clock cycle. An adaptive circuit senses the collected energy that is returned to the logic circuit during the second phase of the clock cycle to determine whether the energy has fallen below a predetermined limit. If so, the adaptive circuit supplies any needed energy during the second phase of the clock cycle. The inductor that collects energy used to operate the logic circuitry and the inherent capacitance of the logic circuitry form a resonant circuit that operates in synchronism with the clock cycle, the inductor storing energy during the first phase and returning the energy to the inherent capacitance of the logic circuitry during the second phase.

Abstract: A method for controlling the execution of a sole target processor or a target processor embedded in a chain of target processor units by a host-processor. The target processor unit includes a shared control register, a shared memory accessible by both the target and host processor and a code memory alterable by the host processor and containing the target processor program. The shared control register includes a single step flag to indicate that the host processor is setting the single step mode of operation for the target processor. The shared control register further includes a clock inhibit flag to permit the target processor to stop execution. Clearing the clock inhibit flag releases the target processor to execute the program in the code memory during which the target processor tests the single step flag to determine whether it should stop execution after one instruction has been executed.

Abstract: A swinging objective retarding immersion lens system and method therefore which provide a low voltage electron beam with high beam current, relatively high spatial resolution, a relative large scan field, and high signal collection efficiency.

Abstract: A sputtering apparatus and method for high rate deposition of electrically insulating and semiconducting coatings with substantially uniform stoichiometry. Vertically mounted, dual rotatable cylindrical magnetrons with associated vacuum pumps form semi-isolated sputtering modules, which can be independently controlled for the sequential deposition of layers of similar or different materials. Constant voltage operation of AC power with an optional reactive gas flow feedback loop maintains constant coating stoichiometry during small changes in pumping speed caused by substrate motion. The coating method is extremely stable over long periods (days) of operation, with the film stoichiometry being selectable by the voltage control point. The apparatus may take the form of a circular arrangement of modules for batch coating of wafer-like substrates, or the modules may be arranged linearly for the coating of large planar substrates.

Abstract: A method and apparatus for processing user-submitted search information to permit a database to be searched regardless of the format and language of the user-submitted information. The user-submitted information is first categorized into one or more categories, where each category is a type of information such as a date, a proper name or a place. For each category pertaining to the user-submitted information, the search is refined by comparing the user-submitted information to a feature table containing specific data types corresponding to each category. From the results of any affirmative comparison with the feature table, a starting location within a corresponding search table is retrieved. The search is further refined by comparing the user-submitted information to the entries of the search table beginning at the starting location. From the results of any affirmative comparison with the search table entries a database address is obtained which is used to obtain a database entry sought after by the user.

Abstract: Methods and systems for interoperating a transaction processing system implementing the presumed abort variation of the two-phase commit (2PC) protocol with a system implementing the presumed nothing variation. The gateway process that is responsible for exporting a transaction branch to a foreign transaction management system from a system implementing the presumed abort variation records whether the foreign transaction manager is implementing the presumed abort variation or the presumed nothing variation. After system failure, the gateway process determines which variation is adopted for a specific transaction branch. If the foreign transaction manager is implementing the presumed abort variation, the transaction manager from which the transaction branch originated communicates with the foreign transaction manager through the gateway process in accordance with the presumed abort variation.