Abstract: A method and system for filtering texture map data for improved image quality in a graphics computer system. The present invention is directed to a method and system for performing texture map filtering for reducing “flickering” and “sparkling” when rendering a relatively small graphics primitives using a texel map of relatively larger area and low color frequency. A footprint area is defined as the area of texel map space that is mapped into one pixel coordinate of display space. One embodiment of the present invention is particularly useful in texture mapping where the footprint area is larger than one. In this instance, during rendering, the change in texel map coordinates (e.g., du, dv) is large for a unit change in screen coordinates (e.g., dx, dy). When obtaining a texel at location (u, v), the present invention performs a color filtering of texels located at distances du and dv away from the texel at location (u, v).

Abstract: An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion.

Abstract: In a computer system, a peripheral graphics device (PGD) accesses a graphics buffer (GB) wherein the GB physical pages can be contiguous or discontiguous. A request is received to allocate memory for a GB of a predetermined size and handle. The number of pages within the size parameter is determined based on the page size used by the computer system and the buffer size needed. A first memory block is allocated for storing the GB and locked to prevent swapping. A starting virtual address of a CPU page table (CPU/PT) is accessed and mapped to a starting logical address to allow traversal of the CPU/PT by a user application. A second memory block is allocated for building a graphics device page table (GDPT) that can be accessed by a PGD. The logical address of each GB page is sequentially accessed and the corresponding physical address of each GB page is determined from the CPU/PT. The logical and physical addresses of each GB page are stored into the GDPT.

Abstract: An input interface circuit for a logic device having a configuration of pull-up and pull-down devices for defining the logic level based on an undriven input signal where the pull-up and pull-down devices are independently and separately programmable to follow the input signal (e.g., a keeper circuit), or follow the inverse of the input signal, or programmed permanently on, or programmed permanently off. The interface circuit can be used to provide a known and programmable output signal for an IC input (or internal line) that does not have a known driving source. By allowing this degree of flexibility, the input interface circuit of the present invention, under programmed control, generates an output signal with positive or negative feedback based on the input signal; or the input interface circuit provides a constant high or constant low signal output, or can oscillate or provide a high impedance response as output.

Abstract: An electrical connection arrangement for a programmable integrated circuit is provided. An electrical device is disposed proximate to a vertical longline which is used for transporting address and data signals. The electrical device includes a vertical address line extending from the device. A horizontally arranged interconnection line is electrically connected to the vertical address line extending from the device. Furthermore, the horizontally arranged interconnection line is programmably connectable to the vertical longline. By electrically hardwire connecting the horizontally arranged interconnection line to the vertical address line extending from the device, only one programmable interconnect point is required to transfer signals from the vertical longline into the electrical device itself. Thus, impedance is reduced, while addressing speed is improved. Also, by adding additional horizontal interconnect lines, the present invention reduces routing barriers.

Abstract: A low voltage driver circuit capable of interfacing with a high voltage node. The high voltage tolerant input/output circuit of the present invention has a first stage operating at a low voltage integrated circuit standard and a second stage capable of operating at both the low voltage and a high voltage integrated circuit standard. The second stage operates at high voltage during the tristate mode and at low voltage during an active mode. The second stage uses an output driver having a p-type pull-up transistor coupled to an input/output pad. The input/output pad interfaces with a high voltage or mixed voltage network. An isolator circuit is coupled between the first stage and the second stage for voltage isolation when the second stage is operating at high voltage. A charger circuit maintains the high voltage on a gate of the p-type pull-up transistor during the tristate mode and the low voltage during the active mode.

Abstract: A field programmable gate array having independently buffered output lines of a CLB for handling critical path situations. One of the CLB's output ports is coupled to a vertical interconnect line and a horizontal interconnect line. Two separate buffers are used to drive these lines. One buffer drives the horizontal interconnect line, while the other drives the vertical interconnect line. One of these lines is used to conduct the output signal that corresponds to the critical path. The other line is used to conduct the output signal onto other branches that are not part of the critical path. Hence, by using a separate buffer to drive the critical path, it is not loaded with the circuits associated with the non-critical branches.

Abstract: A input/output circuit (IOB) within an integrated circuit (IC) device, the output signal driving circuitry of the input/output device contains a dedicated multiplexer on the output path wherein a first and second output signal can be time multiplexed on a single output pad. The multiplexer can also be configured to perform as a high speed gate to realize AND, OR, XOR, and XNOR functions. Within an input/output circuit of a programmable integrated circuit, the system provides a dedicated multiplexer that can select between one of two output signals for sending over the single output pad of the IC device. In lieu of using a programmable memory cell as the select control for the dedicated multiplexer, the system allows a number of lines, including an output clock signal, to be the select control. By using the output clock as the select control, the data signals can be effectively time multiplexed over a single output pad and referenced by the output clock.

Abstract: An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion.

Abstract: A virtual high density architecture having shared memory cells for a programmable integrated circuit (IC) is provided. The architecture includes logic modules, a configuration memory unit (CMU), and a global interconnect memory (GIMU) unit. A logic cycle is divided into a number of time intervals. For each time interval, the CMU outputs information to configure the logic modules and the interconnect structure to realize an individual circuit stage of a circuit. Input and output data pertinent to this individual stage are retrieved from and stored in the GIMU based on addressing information generated from the CMU for each time interval. The CMU continuously reprograms the logic modules and interconnect structure for each time interval to realize different stages of the circuit while information used between stages is stored in the GIMU.

Abstract: A pipeline frame full detection circuit. The present invention is operable within a system that loads configuration data into an integrated circuit (IC) using a serial data stream and transfer mechanism. Configuration data is transferred into the IC in sequential frames of a specified size for a given IC. The first bit of the configuration data contains a frame full indicator. The configuration data is transferred into a shift register circuit and the last bit position(s) of the shift register circuit, in addition to being stored in the shift register circuit, are shifted along a special frame full pipeline to a control unit. The control unit, upon detecting the frame full indicator, asserts a parallel write command that causes the data of the shift register circuit to be parallel transferred to a receiving column of memory. New configuration data can then be serially shifted into the same shift register circuit after a reset signal.

Abstract: An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed, each combining a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snap-back effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical corners are rounded rather than sharp.

Abstract: An input interface circuit for a logic device having a configuration of pull-up and pull-down devices for defining the logic level based on an undriven input signal where the pull-up and pull-down devices are independently and separately programmable to follow the input signal (e.g., a keeper circuit), or follow the inverse of the input signal, or programmed permanently on, or programmed permanently off. The interface circuit can be used to provide a known and programmable output signal for an IC input (or internal line) that does not have a known driving source. By allowing this degree of flexibility, the input interface circuit of the present invention, under programmed control, generates an output signal with positive or negative feedback based on the input signal; or the input interface circuit provides a constant high or constant low signal output, or can oscillate or provide a high impedance response as output.

Abstract: A input/output circuit (IOB) within an integrated circuit (IC) device, the output signal driving circuitry of the input/output device contains a dedicated multiplexer on the output path wherein a first and second output signal can be time multiplexed on a single output pad. The multiplexer can also be configured to perform as a high speed gate to realize AND, OR, XOR, and XNOR functions. Within an input/output circuit of a programmable integrated circuit, the system provides a dedicated multiplexer that can select between one of two output signals for sending over the single output pad of the IC device. In lieu of using a programmable memory cell as the select control for the dedicated multiplexer, the system allows a number of lines, including an output clock signal, to be the select control. By using the output clock as the select control, the data signals can be effectively time multiplexed over a single output pad and referenced by the output clock.

Abstract: A configurable multi-directional buffer circuit for a programmable integrated circuit. The novel buffer circuit is a configurable multi-directional buffer circuit having one pair of inverters and having a first input/output line and a second input/output line and a third input line multiplexed with the first input/output line. The novel buffer circuit is configurable to allow a signal from the first input/output line to be driven over the second input/output line or configurable to allow a signal from the second input/output line to be driven over the first input/output line. The novel buffer circuit also allows a signal over the third input line to be driven over the second input/output line. In either case, only a single pair of inverter circuits are used. In an alternate embodiment, the novel buffer allows signal over a fourth input line to be driven over the first input/output line.

Abstract: A method and apparatus for back-annotating timing constraints onto a logical simulation model of a field programmable gate array circuit includes a process and system for creating equations relating to the sequence of nodes between an input and output or clock input in the logical circuit and equating this to the external timing characteristics of the FPGA circuit. This linear system of equations can then be solved to obtain the individual timing constraints for each node of the circuit within the simulation model.

Abstract: A synchronization mechanism for synchronizing an outside clock with a delayed inside clock is provided. The delayed inside clock is distributed across a network of clock lines within the integrated circuit to deskew the clock signal at the supply points. Although the inside clock signal is deskewed, it is nevertheless delayed compared to an input clock signal provided by a pad of the integrated circuit. A distribution line provided on the periphery of the integrated circuit supplies an outside clock signal that is not substantially delayed compared to the input clock signal at the IC's pad. The synchronization mechanism provides synchronization between the outside clock, as received by an input/output block, and the inside clock. The synchronization is required because configurable logic blocks (CLBs) of the IC are typically referenced by the delayed inside clock.