Abstract: A low voltage driver circuit capable of interfacing with a high voltage node. The high voltage tolerant input/output circuit of the present invention has a first stage operating at a low voltage integrated circuit standard and a second stage capable of operating at both the low voltage and a high voltage integrated circuit standard. The second stage operates at high voltage during the tristate mode and at low voltage during an active mode. The second stage uses an output driver having a p-type pull-up transistor coupled to an input/output pad. The input/output pad interfaces with a high voltage or mixed voltage network. An isolator circuit is coupled between the first stage and the second stage for voltage isolation when the second stage is operating at high voltage. A charger circuit maintains the high voltage on a gate of the p-type pull-up transistor during the tristate mode and the low voltage during the active mode.

Abstract: A field programmable gate array having independently buffered output lines of a CLB for handling critical path situations. One of the CLB's output ports is coupled to a vertical interconnect line and a horizontal interconnect line. Two separate buffers are used to drive these lines. One buffer drives the horizontal interconnect line, while the other drives the vertical interconnect line. One of these lines is used to conduct the output signal that corresponds to the critical path. The other line is used to conduct the output signal onto other branches that are not part of the critical path. Hence, by using a separate buffer to drive the critical path, it is not loaded with the circuits associated with the non-critical branches.

Abstract: A input/output circuit (IOB) within an integrated circuit (IC) device, the output signal driving circuitry of the input/output device contains a dedicated multiplexer on the output path wherein a first and second output signal can be time multiplexed on a single output pad. The multiplexer can also be configured to perform as a high speed gate to realize AND, OR, XOR, and XNOR functions. Within an input/output circuit of a programmable integrated circuit, the system provides a dedicated multiplexer that can select between one of two output signals for sending over the single output pad of the IC device. In lieu of using a programmable memory cell as the select control for the dedicated multiplexer, the system allows a number of lines, including an output clock signal, to be the select control. By using the output clock as the select control, the data signals can be effectively time multiplexed over a single output pad and referenced by the output clock.