Abstract: The card guide with hook/card lock as disclosed is designed to prevent a printed circuit board (PCB) from being disengaged without first moving the mechanical card locking hook an adequate distance. When the mechanical card locking hook is flexed to disengage a PCB, the card lock will move only enough to allow the PCB to be disengaged and removed. The card guide has a built in fixed stop to prevent the extended card lock from deforming or breaking during disengagement of a PCB.
Abstract: In order to accomplish the object of the present invention there is provided a network independent clocking (NIC) circuit which allows a local synchronous master to exchange data with a local data adpater. The NIC circuit includes a phase measuring block for continually generating a local phase difference indicator, where the local phase difference indicator indicates a phase relation between the local data adapter and the local synchronous master. The local phase difference indicator is transmitted to a remote data adapter. Back locally, a phase difference indicator is received from a remote data adapter. A baud clock is generated and used to transfer data from the data adapter to the synchronous master, the baud clock generator uses the phase difference indicator to recreate the phase difference between the remote data adaper and the remote synchronous master.
Abstract: A printer plate locating device used in the alignment of printer plates with respect to a screen or stencil holder of a screen printing machine. The present invention is particularly useful when used in a multi-station printing machine where the printing machine sequentially moves the printer plates into a printing station to affect the printing or image transfer. The present invention consists of two securely connected rigid plates and a system of actuators. The mounting plate 1 acts as a support or structural member for the rest of the apparatus. The alignment plate, being smaller in size than the mounting plate, provides edges against which the substrate locating devices of the printer plate make contact. In operation, the present invention is fastened to the screen holder in place of a screen or stencil on the first station of the machine.
Abstract: A circuit for detecting and verifying a presence of a terminating device for a high speed data transmission line. The circuit contains a first cable detector which generates a first signal if a first cable is present. A second cable detector generates a second signal if a second cable is present. The terminating device is contained in a plurality of resistor packs, each of the which contains an extra resistor. A terminating device detector senses the extra resistor presence, thereby detecting the presence of the resistor packs. The terminating device detector generates an ALL-EQUIPPED signal and a NON-EQUIPPED signal, the ALL-EQUIPPED signal is generated when all of the plurality of resistor packs are present, the NON-EQUIPPED signal is generated when all of the plurality of resistor packs are absent. Finally, a verifier circuit receives the first signal, the second signal, the ALL-EQUIPPED signal and the NON-EQUIPPED signal.
Abstract: An assembly for holding a squeegee blade provides a levelness control of the squeegee blade and a pressure control on the squeegee blade. The assembly includes a wedge having a length approximately equal to that of the squeegee blade. The wedge also has a right triangle shape along its longitudinal axis. The wedge is positioned between an upper stationary body and the squeegee blade. There is also a pressure adjustment for moving the wedge in either direction along its longitudinal axis, such that the motion of the wedge produces pressure on the squeegee blade; thus, providing the pressure control. The leveling control is accomplished by a micrometer attached to a rigid plate. The micrometer being rotatable along its longitudinal axis. A gear, which is attached to the upper stationary body, is rotatable about a pivot point on the ridged plate by the rotation of the micrometer.
Abstract: A single circuit for detecting a synchronization pattern in a serial data stream. Subsequent to detecting the synchronization pattern, the single circuit generates the control signals for converting the serial data to a parallel format and loading the parallel data into a first-in-first-out (FIFO) memory. The single circuit includes a controller arranged to receive the serial data stream. A counter is connected to the controller. When the counter is detecting the synchronization pattern and the synchronization pattern is being received, the counter is incremented. Absent the synchronization pattern being received, the counter is reset to a predetermined starting point. Subsequent to detecting the synchronization pattern, the counter generates a load signal. The single circuit further includes a pulse generator arranged to receive the load signal from the counter and generate a pulse of duration equal to a bit period of the serial data stream.
Abstract: The circuit of the present invention provides a signal which allows data to be transferred between a first synchronous system to a second synchronous system. Where the first synchronous system is a Time-Division-Multiplexing (TDM) system and the second synchronous system is a Microprocessor system. The transfer is allowed at the end of the assigned time slot provided that the microprocessor is not accessing the data. If the microprocessor is accessing the data, then the transfer is delayed for three clock cycles of the TDM clock. After the delay, if the microprocessor is still accessing the data, the transfer is delayed again. The delaying continues until the microprocessor is no longer accessing the data, at which time the transfer is allowed.
Abstract: An interface circuit which connects a Digital-Signal-Processor (DSP) to a serial controller. The interface circuit includes a bi-directional multiplexer which converts the separate address and data busses of the DSP to the multiplexed data and address bus of the serial controller. A timing generator is included for keeping track of the number of clock cycles in the present access. A decoder connected to the timing generator decodes the number of clock cycles and generates the appropriate control signals to both the serial controller and the DSP.
Abstract: A configuration control of a duplex real time processor system without the need for third party configuration control circuitry is provided. A remote control system is connected to duplex real time processors via a pair of serial data links. These data links are configured in an active/standby arrangement. The serial links are connected to the duplex real time processors in such a way that each processor of the pair determines independently whether to assume an active or a standby role. Each real time processor bases this decision upon the identity of the serial link from which it is receiving data transmitted by a remote control system.
Abstract: The circuit of the present invention provides a signal which allows data to be transferred between a first synchronous system to a second synchronous system. Where the first system is a Time-Division-Multiplexing (TDM) system and the second system is a Microprocessor system. The transfer is allowed after three or four memory cycles of the Microprocessor system after receiving the end of time slot signal. This invention requires that the Microprocessor system access the Time-Division-Multiplexed system as an Input/Output (I/O) device.
Abstract: A circuit for determining the validity of the frequency of a clock signal is shown. The circuit includes a frequency detector circuit having a synchronizer which receives the clock signal and synchronizes it to a synchronous clock signal. A pattern detector detects an error pattern from the synchronizer and generates an error signal which is transmitted to a latch and stored.
Abstract: A circuit for dividing a clock signal by two and one-half (2.5) is shown. The divide by two and one-half (2.5) circuit includes a clock selector circuit arranged to output a selected polarity of the first clock signal. A ring counter arranged to receive the clock selector circuit output signal, and output a signal that has a period of 3 times (3.times.) the signal received from the clock selector circuit. A divide by two circuit connected to the ring counter circuit and to the clock selector circuit. The divide by two circuit divides the ring counter output signal by two to produce an output signal. The divide by two output signal is then fed back to the clock selector circuit to regulate the selection of the first clock signal polarity, causing the ring counter to output a clock signal with a period of two and one-half times (2.5.times.) the first clock signal.
Abstract: A Unique Phase Difference Measuring Circuit which measures the phase difference between a reference pulse train and a slave pulse train. The present invention includes delay lines that determine the phase difference between the pulse trains which can be read directly by a microprocessor.
December 19, 1988
Date of Patent:
May 15, 1990
AG Communication Systems Corporation
George K. Tarleton, Robert J. Abrant, Bruce A. Oltman