Abstract: A method for manufacturing package structure integrated circuit chips having a heat spreader is disclosed. A wiring substrate is first provided. An integrated circuit chip, having a first surface and a second surface, is then electrically and mechanically connected to the wiring substrate via a first set of solder joints. A heat spreader is subsequently connected to the second surface of the integrated circuit chip via a second set of solder joints. The heat spreader includes an adhesion-promotion layer on a silicon layer.

Abstract: An improved method of estimating the square root, reciprocal square root, and reciprocal of an input value in a computer system. The input value, after being normalized, is used to select a pair of constants from a table. The constants are based on a linear approximation of the function for each interval of the input value, offset to reduce a maximum error value for a given interval. The estimated function is calculated by adding or subtracting the product of a part of the normalized input value and the first constant from the second constant. In one implementation, the input value is normalized within the range 1.ltoreq.x<2, and one lookup table is used, having an interval size of 1/32. In a further preferred embodiment, only a lower order part of the mantissa is used in the multiply-add operation, to reduce the number of bits required (the high order part of the mantissa is used to select the constants from the table). In another implementation, the input value is normalized within the range 0.5.ltoreq.

Abstract: A multiport memory cell having a reduced number of write wordlines is disclosed. The multiport memory cell capable of simultaneously reading data from and writing data to a storage cell comprises a storage cell for storing data, a decoder, write wordlines, write bitlines, read wordlines, and read bitlines. The write wordlines and the write bitlines are utilized to input write data into the storage cell. The read wordlines and the read bitlines are utilized to output data from the storage cell. The write bitlines are directly coupled to the storage cell, and some or all of the write wordlines are coupled to the storage cell via the decoder for the purpose of wire reduction. Similar to the write bitlines, all the read bitlines and read wordlines are directly coupled to the storage cell.

Abstract: Series-connected stacked PFETS are employed in an off-chip driver output stage. When the output driver is enabled, the gate of the PFET transistor directly connected to the output is biased by a latch at a voltage level of either one threshold voltage above ground or one threshold voltage below the power supply, depending on the data signal. This provides overvoltage protection even for overshoots and undershoots of one threshold voltage or less, and provides overvoltage protection below the threshold voltages required to activate conventional overvoltage protection devices. Tight tolerances for maximum gate voltages may thus be achieved, and smaller devices having thinner gate oxides utilized in the off-chip drivers of a processor or other device.

Abstract: Each execution unit within a superscalar processor has an associated completion table that contains a copy of the status of all instructions dispatched but not completed. A central completion table maintains the status of every dispatched instruction as reported by the dispatch unit and the individual execution units. Execution units send finish signals to the completion table responsible for retiring a particular type of instruction. The central completion table retires instructions that may cause an interrupt and instructions whose results may target the same register. The execution units' associated completion tables retire the balance of the instructions and the execution units send instruction status to the central completion table and to each execution unit. This reduces the number of instructions that are retired by the central completion table, increasing the number of instructions retired per clock cycle.

Abstract: Described is an apparatus for eliminating early retrying of PAAM address conflicts on a system bus with multiple processors connected by a non-master processor, by comparing addresses of the current master processor to the next transaction to be issued by the non-master processor. If the addresses are the same and a PAAM window is detected, the non-master processor will switch the next transaction type to be issued, to a null type transaction. Even though the addresses match, the PAAM window is ignored for a null type transaction. The null transaction type insertion by the non-master processor reduces the latency of a PAAM self retried operation and avoids a possible livelock condition by breaking the processors out of the livelock. This allows the processors to stop retrying and leave the bus. The processors are able to immediately arbitrate instead of delaying past the astat window and increasing bus latency.

Abstract: A data processing system includes at least a first processor and a second processor that each have a respective translation lookaside buffer (TLB). In response to detection by the second processor of a TLB entry invalidation request, the second processor marks at least one memory referent instruction that is being processed by the second processor and invalidates a TLB entry in the TLB of the second processor. In response to receipt of a synchronization request at the second processor, the second processor indicates to the first processor that the second processor has invalidated the TLB entry if the second processor has completed processing the marked instruction. During the interval between receipt of the synchronization request and indicating to the first processor that the second processor has invalidated the TLB entry, the second processor continues to process instructions, including fetching instructions for processing.

Abstract: A multimedia facility within a processor employs a crossbar to perform operations requiring byte reordering. Prior to the cycle in which an instruction is executed, the instruction is checked to determine if the instruction is a predetermined type of instruction. If not, the operand which should contain encoded crossbar selects is filled with zeros before presentation to the crossbar select generation logic. If the instruction is one of the predetermined type of instructions, however, the real operand containing the encoded crossbar selects is presented to the crossbar select generation logic. As a result, only crossbar selects which designate byte 0 of the source operand as the source need to be qualified with a signal verifying the instruction being executed. The fanout of the qualification signal is thus reduced to an acceptable level, at which 1 cycle latency and 1 cycle throughput may be achieved.

Abstract: A novel SRAM construction allows for reduced power consumption by conditionally restoring only those memory cells which are evaluated (subjected to a read or write operation). The device includes a memory array containing an arbitrary number of memory cells, a plurality of word lines, and a plurality of predecoded address lines which allow selection of one of said word lines, wherein the memory cells are arranged in groups, each group having a bit line connected thereto. A precharge circuit is connected to the bit lines, and restores a given one of the memory cells after the evaluation operation. The predecoded address lines carry encoded information regarding an address associated with the evaluated memory cell, and a decoder identifies the address to determine which of the word lines should be used to access the evaluated cell. In one embodiment, the precharge circuit is responsive to control logic associated with the address (and carried on the predecoded address lines).