Abstract: A system and method have been provided that permit a mobile station to enter a deep-sleep slotted mode of operation in response to detected patterns of low traffic communications. A record of traffic communications is maintained at either the mobile station, or in the wireless communications network. Analysis of the record indicates whether the mobile station should be operated in the deep-sleep mode. Then, the deep-sleep mode, with a larger period between control messages, is negotiated. In some aspects of the invention, the period between control messages is a function of the likelihood of a traffic communication occurring.

Abstract: A switching regulator having a control circuit that automatically senses when a low power mode should be initiated without the use of expensive external components nor an extensive amount of external components is disclosed herein. The switching regulator includes an input switching device, a driver, an inductor, a first output switching device, a second output switching device and an output node. The control circuit includes a low power switching device connected to the output node and the second end of the inductor. An amplifier connects the low power switching device and the first output switching device. A first current mirror couples to the amplifier to mirror the difference between the output current through the output load and the current supplied at the second end of the inductor. A second current mirror couples to the first current mirror to mirror the current difference through a current source and a capacitor connected in parallel across the current source.

Abstract: A programmable gain amplifier using metal-oxide-semiconductor (MOS) devices to approximate exponential gain characteristic with linear control signals is disclosed. According to one embodiment, the programmable gain amplifier (300a-300b) may include a capacitive switching circuit (304a-304b), a capacitive switching circuit (306a-306b), and an operational amplifier (302a-302b). Capacitive switching circuits (304a-304b and 306a-306b) may receive an analog input voltage through sample switches (308a-308b and 310a-310b). Capacitive switching circuit (304a-304b) receives an output from operational amplifier (302a-302b) through feedback switch (312a-312b). The programmable gain amplifier (300a-300b) may include a few additional unit capacitors which can allow larger gain ranges or more steps for a given range without a large increase in chip size.

Abstract: An image processing apparatus (200) for a charge coupled device including analog front end circuitry having optical black and offset correction, whereby the offset and optical black correction circuit is programmable. The present invention includes a first circuit (202, 204, 206, 208, 210) to sample the incoming optical black signal output from a CCD. This first circuit includes a correlated double sampler (202) coupled to a first programmable gain amplifier (204). An adder (206) connects between the first programmable gain amplifier (204) and a second gain amplifier (208) for adding in the optical black offset to the optical black signal input from the CCD. A second circuit (212, 214) includes a reverse programmable gain amplifier (212) connected to the output of the second programmable gain amplifier (208) to amplify the optical black level inversely proportional to the gain from the second programmable gain amplifier (208).

Abstract: A system is provided for finding the result of a binary operation performed on an array of values, along with its address, in a storage-efficient manner. The system is based on a binary tree structure having a pipeline of binary operators and corresponding multiplexers and storage elements to store the outputs of the multiplexers in addition to the partial addresses of the outputs represented by the outputs of the binary operators. Each computation stage adds one more bit of address until the address is completely known at the last computation stage. The invention reduces the amount of storage required for keeping track of the addresses that are the result of the binary operation.

Abstract: A codifier/decodifier (CODEC) filter circuit (250) connected in a subscriber line interface circuit (202) includes a transmit section (264, 262, 260) for converting differential voltage audio transmit signals representing voice transmissions from the subscriber instrument (202) into encoded digital data for transmission to the digital switching network. A receive section (254, 252) coupled between the digital switching network and subscriber instrument (202) within CODEC (250) for converting encoded digital data representing voice signals switched through the digital switching network to differential voltage audio receive signals for transmission to the subscriber instrument (202). The subscriber loop and subscriber instrument (202) reflect the digital voltage audio signals to the transmit section (264, 262, 260).

Abstract: A threshold voltage extraction circuit. The circuit includes a first current mirror having a first transistor and a second transistor. A holding circuit has an output adapted to control a current though the first current mirror by operating to maintain substantially equal the voltages at a first input thereof and at a second input thereof. A third, MOS transistor having a source and a gate, and a resistor circuit, together adapted to generate a voltage which is a multiple of a source-gate threshold voltage of the third transistor, are coupled to the second transistor and to the first input of the holding circuit. A fourth, MOS transistor coupled to the first transistor and to the second input of the subtracting circuit through a second resistor circuit is adapted to generate a threshold voltage across the second resistor circuit, by the operation of the holding circuit.

Abstract: An image processing apparatus (800) for a charge coupled device having hot/cold pixel and line noise filtering is disclosed which provides optical black and offset correction. The present invention teaches an offset and optical black correction circuit having a digital filter to obtain noise-free optical black correction for charge-coupled devices such that a digitally programmable bandwidth exists. The sum of the channel offset and optical black level is averaged for a given number of lines having a number of optical black cells per line and this sum passes through a digital filter. Moreover, the channel is digitally calibrated to obtain a user programmed ADC (810) output which corresponds to that average.

Abstract: A Sigma-Delta Analog-to-Digital Converter (ADC) having efficient dithering that removes the idle channel tones of the sigma-delta converter is disclosed herein. These idle channel tones are reduced or removed by stretching the threshold window of the multi-level quantizer. A dithering sequence is added by stretching the thresholds window randomly. The randomly stretched window destructs the periodicity of sigma-delta ADC modulator's output sequence and, thus, removes the idle channel tones. Compared with conventional methods, the Sigma-Delta ADC in accordance with the present invention has less SNR penalty and is simple to implement. Moreover, the sigma-delta ADC in accordance with the present invention has a higher allowed input dynamic range and higher signal-to-noise-plus-distortion-ratio (SNDR) than conventional modulator dithering schemes.

Abstract: A Universal Serial Bus (USB) modem (14) in which reassembly and segmentation operations are performed outside of the host computer (12) is disclosed. A USB interface device (30) is coupled to a digital signal processor (DSP) (32) in the modem (14), and contains a shared memory (44) in which bulk endpoints (240) are established, at which ATM packet header and payload data are stored prior to transmission. An ATM transmit controller (132) retrieves the header portion of the ATM packet from a transmit endpoint (240) and stores the information in registers (252, 254, 256) in the ATM transmit controller (132). A four-byte ATM cell header is then transmitted to byte buffers (268) and to the DSP (32) for transmission over the communications facility. Afterwards, payload data is retrieved from the transmit endpoint (240) in shared memory (44), and forwarded to byte buffers (268) for transmission.

Abstract: A system for data communication is disclosed that comprises a hybrid circuit (220) that receives a signal. A switched gain circuit (204) coupled to the hybrid circuit (220) receives the signal from the hybrid circuit (220). A receiver circuit (206) coupled to the switched gain circuit (204) receives the signal from the switched gain circuit (204). The switched gain circuit (204) adjusts the power of the signal transmitted to the receiver circuit (206). More specifically, the switched gain circuit (204) detects the power of the signal received from the hybrid circuit (220), and adjusts the power of the signal transmitted to the receiver circuit (206) based upon the power of the signal received from the hybrid circuit (220). A method for data communication is disclosed. A signal is received using a hybrid circuit (220). The signal is transmitted to a switched gain circuit (204) coupled to the hybrid circuit (220). The power of the signal is adjusted using the switched gain circuit (204).

Abstract: An image processing apparatus for a charge coupled device including analog front end circuitry having optical black and offset correction, whereby the an offset and optical black correction circuit has a digitally programmable bandwidth is disclosed herein. The image processing apparatus includes a sampling circuit to sample the incoming optical black signal output from a CCD. The sampled signal is filtered through an analog-to-digital converter for processing by a digital detector circuit which detects the average optical black level of the sampled signal. The sum of the channel offset and optical black level present at the output of the digital detector circuit as a digital error signal is averaged for a given number of lines and optical black cells per line by a digital averager included within the digital detector circuit. Moreover, calibration logic digitally calibrates the channel to obtain a user programmed ADC output which corresponds to that average.

Abstract: A high voltage integrated circuit operable in a system having a low voltage reference, a high voltage reference, and a ground, for providing an output voltage higher than the high voltage reference. The integrated circuit includes a high voltage ground reference circuit, operable to provide a high voltage ground reference node. Also included is an oscillator, operable to provide a clock signal, the oscillator being connected to the high voltage reference and to the high voltage ground reference node. An isolated charge pump circuit is provided, operable to generate the output voltage and isolated in the integrated circuit from other circuitry.

Abstract: A programmable delay circuit (100) maximizes processor bandwidth to external peripherals by eliminating wait state addition as the only way for satisfying timing requirements. Circuit (100) includes a programmable delay chain (102) connected to a hysteresis circuit (150). A processor control signal is fed into the programmable delay chain (102) which includes at least one switch (104-116) and at least one resistive element (118-126) connected together. A first feedback circuit (128) connects the output of the programmable delay chain (102) to the input (IN2) of the first embodiment (100) to keep the falling edge of the control signal the same without any significant added delay. The hysteresis circuit (150) which provides a stable signal connects to an output driver (180) for driving the processor control signal.

Abstract: A Universal Serial Bus (USB) modem (14) having two operating modes, namely Digital Subscriber Loop (DSL) mode and a voice-band mode, is disclosed. A USB interface device (30) is coupled to a digital signal processor (DSP) (32) and contains a shared memory (44) in which USB endpoints are established for data communication. In the DSL mode, an ATM receive controller (134) receives each ATM cell from the DSP (32) and interrogates the ATM cell header to determine the virtual connection to the corresponding cell, and then forwards the payload portion of the ATM cell, but not the ATM cell header. In the voice-band mode, the ATM receive controller (134) and ATM transmit controller (132) operate in a simple streaming mode. A host interface controller (135) is also provided, by way of which facsimile communications are carried out simultaneously with DSL communications, or in separate sessions relative to voice-band data communications.

Abstract: An image processing apparatus for charge coupled device (CCD) and video inputs in a digital camera or for a digital camcorder is disclosed which provides optical black and offset correction for CCD inputs. A sampling circuit, including correlated double sampler (CDS) (402) and programmable gain amplifier (450), samples the image input signal and the video input signal. CDS (402) includes a single-ended amplifier (404) and a differential amplifier (406). The single-ended amplifier (404) functions such that it is only operable during an CCD signal input; otherwise, the single-ended amplifier (404) is bypassed such that a video signal is only sampled by the differential amplifier (406). For CCD signals, the single-ended amplifier (404) samples the reference level of the pixel and holds it during the video interval. The differential amplifier (404) samples both the output of the single ended amplifier (404) and the video level of the same pixel.

Abstract: The present invention relates to a source driver circuit (200) for driving a thin film transistor liquid crystal display (TFT-LCD) panel. The source driver circuit (200) provides several different operating modes for the driver to lower the power consumption of a TFT-LCD module while still providing a wide analog voltage range to the liquid crystal display elements. A mode signal (MODE) switches the driver from gray scale to standby mode wherein the internal resistive digital to analog converter (202), decoder/output voltage drivers (210) and output buffer amplifiers (212) are powered down. In addition, only the most significant bit of data corresponding to red, green and blue are transferred to a sample and hold register (206, 208). Output cells (216), substituting for the decoder/output voltage drivers, receive one-bit data from hold registers (208) and provide voltage at the output of the driver circuit (200).

Abstract: A bi-cosine filter having a scaling technique to process images for up-scaling that does not lead to loss of the high frequency content of the generated image nor leads to image artifact known as waxing and waning is disclosed. The two tap filter (100) includes an input node (102) coupled to receive the image data. A first multiplier (104) couples to receive a first coefficient (C0) and the image data input. The first multiplier (104) multiplies the image data input by the first coefficient (C0) to provide a first product. The image data input is feed through a delay element (106) to delay the image data by a predetermined time period. Delay element (106) connects to a second multiplier (108) that couples to receive a second coefficient (C1). The second multiplier (108) multiplies the time-delayed image data by the second coefficient (C1) to provide a second product.

Abstract: A temperature sensing system (30) that providing at least one detect signal related to temperature in an integrated circuit is presented. This system uses one thermal sensing circuit (40) to detect two or more temperature thresholds (t2, t3) and differentiates the temperature thresholds using time multiplexed logic control. The system (80) capable of detecting more than two temperatures includes the thermal sensing circuit (90) and a decode circuit (92) with at least one detect latch (100). Optionally, the system may include a hysteresis circuit (60). The thermal sensing circuit (40), connected to the integrated circuit, generates a detect signal (D4) in response to the a temperature selection signal (T1). This flexible on-board temperature monitoring solution reduces the cost of thermal feedback sensing by reducing die area and improves the correlation of detected temperatures. In addition, this solution reduces the possibility of mismatch and tracking errors between two or more sense elements.

Abstract: A lattice-based second-order allpass filter (200) providing a digital filter, absent of limit cycles, includes interconnected quantizers(214, 224), delays (232, 240), multipliers (210, 220), and adders (208, 216, 228) for defining a transfer function, where the circuit corresponds in order and values to intrinsic values of the transfer function. The quantizers are connected in series after the multipliers to eliminate any double precision additions which give rise to the appearance of parasitic oscillations. The savings in hardware results from locating the quantizers after the multipliers; thus, eliminating all double precision additions that are mandatory in the classical second-order lattice structure. The second-order allpass filter coefficients that retain the limit-cycle-absent property of the filter correspond to specific guidelines.