Abstract: A novel Finite Impulse Response (“FIR”) filter (100) is provided with. A master/slave sample and hold architecture is employed. In this architecture, an input signal (VIN) is coupled to an input of a master sample and hold circuit (104). At least two slave sample and hold circuits (114, 118) connect to the master output. The slave sample and hold circuits (114, 118) operate at 1/k times the clock rate of the master sample and hold circuit (104), where k equals the number of slave sample and hold circuits (114, 118). A first multiplexer (126) multiplexes the slave outputs together. At least one tap block (129, 179, 207) is coupled to the first multiplexer (126) includes a multiplier (132, 180, 210), a summer (142, 142, 216), at least two slave sample and hold circuits (152, 154, 188, 190, 224, 226) and a second multiplexer (164, 200, 236). The slave sample and hold circuits (152, 154, 188, 190, 224, 226) run at 1/k times the clock speed of the master sample and hold circuit (126).

Abstract: An improved counter register (30) and method of transferring data from a host data bus (29) controlled by a first clock source (BCLK) to the cycle timer (18) controlled by a second clock source (NCLK) which frees the host data bus (29) to perform other functions while a clock synchronization process occurs to allow the data (24) to be written to the counter register (30) or read from the counter register (30). This synchronization scheme is such that at any time the host data bus (29) may read data (25) from the cycle timer (18) and retrieve the current counter register value. In the alternative, at any time, the host data bus (29) may write to the cycle timer (18) and it will receive this data (24) immediately. In either case, the data is transferred immediately without the host data bus (29) having to wait for synchronization across the aforementioned clock boundary.