Abstract: The drift between a write pointer and a read pointer processing packets of data through a FIFO buffer is compensated for by adjusting the start of the read pointer relative to the write pointer. The FIFO buffer is sized to include a number of storage cells equal to the product of the maximum frequency offset between the write clock and read clock and the maximum number of data units in a packet. Initially the start of the read pointer is delayed, relative to the write pointer, by a portion of the number of storage cells in the FIFO. During the processing of a data packet it is determined whether the read pointer is drifting toward or away from the write pointer. If the read pointer is drifting away from the write pointer, for subsequent data packets, the read pointer is started almost immediately after the write pointer writes to the first storage cell in the FIFO.

Abstract: A semiconductor integrated circuit device includes a first delay circuit delaying a first clock signal, a second delay circuit delaying a second clock signal which has an inverted phase with respect to the first clock signal, a phase comparator outputting a phase error signal based on a comparison of the first clock signal and a feedback signal corresponding to an output signal from the first delay circuit, a delay control circuit generating a delay control signal based on the phase error signal, for variably controlling a delay quantity of the first and second delay circuits, and a timing adjusting circuit variably controlling a delay quantity of the second delay circuit by supplying the delay control signal to the second delay circuit at a timing synchronized to the second clock signal.