Patents Represented by Law Firm Armstron, Westerman, Hattori, McLeland & Naughton
  • Patent number: 5849667
    Abstract: A high critical temperature and high critical current density superconductor is disclosed which contains a metal oxide expressed by the following formula (I):(R.sup.1.sub.1-x, Ba.sub.x)Ba.sub.2 Cu.sub.3 O.sub.d (I)wherein R.sup.1 stands for at least one element selected from the group consisting of La, Nd, Sm, Eu and Gd, x is a number greater than 0 but not greater than 0.5 and d is a number between 6.2 and 7.2. Fine phases of RE211, RE422 and/or a metal oxide expressed by the formula (R.sup.2.sub.1-z, Ba.sub.z) (Ba.sub.1-y, R.sup.2.sub.y).sub.2 Cu.sub.3 O.sub.p (R.sup.2 =La, Nd, Sm, Eu or Gd) may be dispersed in a matrix of the matrix phase of the formula (I). The above superconductor may be obtained by cooling a melt having a temperature of 1,000.degree.-1,300.degree. C. and containing R.sup.1, Ba, Cu and O at a cooling rate of 5.degree. C./hour or less under a partial pressure of oxygen of between 0.00001 and 0.05 atm, followed by annealing at 250.degree.-600.degree. C. in an oxygen atmosphere.
    Type: Grant
    Filed: July 19, 1996
    Date of Patent: December 15, 1998
    Assignees: International Superconductivity Technology Center, Railway Technical Research Institute, Shikoku Denryoku Kabushikigaisha, Tosoh Corporation
    Inventors: Masato Murakami, Sang-Im Yoo, Naomichi Sakai, Hiroshi Takaichi, Takamitsu Higuchi, Shoji Tanaka
  • Patent number: 5731730
    Abstract: In a magnetic disk drive in which an analog signal having symmetrical positive and negative odd levels with respect to a zero-level is read out of a magnetic disk by a head, the read analog signal is processed by an AGC circuit and a low pass filter, the processed analog signal is converted into a digital signal by an A/D converter, and the digital signal is demodulated by a demodulator, a zero-level setting circuit for the A/D converter is comprised of: a reference voltage generator for the A/D converter; a zero-level error detector between the read signal and the reference voltage; an accumulator for accumulating the zero-level error from the zero-level error detector; and an equalizer for equalizing the zero-level of the A/D converter to the reference voltage in accordance to an output signal from the zero-level error accumulator. As a result, the conversion accuracy of the A/D converter is improved while employing a small number of bits.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: March 24, 1998
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Muto