Patents Represented by Law Firm Arnold, Whiteh & Durkee
  • Patent number: 5574673
    Abstract: A parallel architecture for implementing a digital sequence generator is provided, which contains taps connected to selected fixed memory cells and the taps of the logic circuitry are switched among the cells. The architecture disclosed and claimed herein generates an identical sequence while consuming substantially less power than a linear feedback shift register implementation. The parallel architecture may also be used to implement a parallel shift register in other applications.
    Type: Grant
    Filed: November 29, 1994
    Date of Patent: November 12, 1996
    Assignee: Board Of Regents, The University Of Texas System
    Inventor: Menahem Lowy